Implementation - 2024.2 English

Vitis Libraries

Release Date
2025-04-14
Version
2024.2 English

The input matrix should ensure that the following conditions hold:

  1. No duplicate edges
  2. compressed sparse column/row (CSC/CSR) format

The algorithm implementation is shown in the following figure:

Figure 1 : convert CSC CSR architecture on FPGA

Figure 1 Convert CSC CSR architecture on FPGA

As seen from the figure:

  1. Firstly, call the Module calculate degree to generate the transfer offset array.
  2. By using the input offset and indice arrays and also the calculated new offset array, generate the new indice array.