The complete list of required parameters for the VSS FFT is shown in L2/include/vss/vss_fft_ifft_1d/vss_fft_ifft_params.cfg. Please edit the parameters in this file to configure the VSS FFT. The user can add to the [aie] section of the cfg file for other options that they want to pass directly to the aiecompiler. Please see API reference on vss_fft_ifft_1d_graph.hpp for details on the AI Engine configurable parameters for VSS Mode 1 and see the vss_fft_ifft_1d_front_only_graph.hpp for the parameters for VSS Mode 2.
| [Category] Parameter | Description |
|---|---|
| part | Name of the part that the VSS should compile for |
| freqhz | Frequency of the internal PL components of the VSS (In Hz) |
| [aie] enable_partition | Configuration of the range of columns that you want to place the compiled AIE kernels. Please do not change the name of the aie partition. |
| [APP_PARAMS] DATA_TYPE | Used to set TT_DATA described in API Reference |
| [APP_PARAMS] TWIDDLE_TYPE | Used to set TT_TWIDDLE described in API Reference |
| [APP_PARAMS] POINT SIZE | Used to set TP_POINT_SIZE described in API Reference |
| [APP_PARAMS] FFT_NIFFT | Used to set TP_FFT_NIFFT described in API Reference |
| [APP_PARAMS] SHIFT | Used to set TP_SHIFT described in API reference |
| [APP_PARAMS] API_IO | Used to set TP_API described in API reference |
| [APP_PARAMS] ROUND_MODE | Used to set TP_RND described in API reference |
| [APP_PARAMS] SAT_MODE | Used to set TP_SAT described in API reference |
| [APP_PARAMS] Twiddle Mode | Used to set TP_TWIDDLE_MODE described in API reference |
| [APP_PARAMS] SSR | Used to set TP_SSR described in API reference |
| [APP_PARAMS] AIE_PLIO_WIDTH | Sets the PLIO width of the AIE-PL interface |
| [APP_PARAMS] VSS_MODE | Sets the mode of decomposition of the VSS. Choose between 1 and 2. |
| [APP_PARAMS] ADD_FRONT_TRANSPOSE | Use to indicate whether to include a data rearrangement block at the input side of the VSS. Refer to design notes for more details. |
| [APP_PARAMS] ADD_BACK_TRANSPOSE | Use to indicate whether to include a data rearrangement block at the output side of the VSS. Refer to design notes for more details. |