While the term Super Sample Rate strictly means the processing of more than one sample per clock cycle, in the AIE context, it is taken to mean an implementation using parallel kernels to improve performance at the expense of additional resource use. In the FFT, SSR operation is controlled by the TP_PARALLEL_POWER template parameter. This parameter is intended to improve performance and also allow support of point sizes beyond the limitations of a single tile. Diagram Applying Design Constraints shows an example graph with TP_PARALLEL_POWER set to 2. This results in four subframe processors in parallel each performing an FFT of N/2^TP_PARALLEL_POWER point size. These subframe outputs are then combined by TP_PARALLEL_POWER stages of radix2 to create the final result. The order of samples is described in the note for TP_API above.
The TP_PARALLEL_POWER parameter allows a trade of performance for resource use in the form of tiles used. The following table shows the tile utilization versus TP_PARALLEL_POWER assuming that all widgets co-habit with FFT processing kernels.
| TP_PARALLEL_POWER | Number of Tiles |
|---|---|
| 0 | 1 |
| 1 | 4 |
| 2 | 12 |
| 3 | 32 |
| 4 | 80 |