SSR - SSR - 2025.2 English

Vitis Libraries

Release Date
2026-02-09
Version
2025.2 English

The DFT supports an SSR, using the TP_SSR template parameter, which allows for multiple cascaded kernel paths to operate in parallel. Kernels in one SSR rank should receive same input data as all other SSR ranks, however, each rank of SSR will produce an equal split of the DFT output. The outputs for each SSR should be interleaved back together to produce the final output of the DFT.

DFT Kernel Connections with TP_SSR=2 and TP_CASC_LEN=3 shows the input and output graph port connects for a cascaded SSR DFT.

../../../_images/dft_ssr_3_2.png

Figure 4 DFT Kernel Connections with TP_SSR=2 and TP_CASC_LEN=3