Fields - 2024.1 English

Vitis Libraries

Release Date
2024-05-30
Version
2024.1 English
port <input> inA [TP_CASC_LEN *TP_SSR]

The input A data to the function. This input is a window of samples of TT_DATA_A type. The number of samples in the window is described by TP_INPUT_WINDOW_VSIZE_A, which is derived from (TP_DIM_A / TP_SSR) * (TP_DIM_AB / TP_CASC_LEN). There are TP_CASC_LEN * TP_SSR input A ports.

port <input> inB [TP_CASC_LEN *TP_SSR]

The input B data to the function. This input is a window of samples of TT_DATA_B type. The number of samples in the window is described by TP_INPUT_WINDOW_VSIZE_B, which is derived from (TP_DIM_AB / TP_CASC_LEN) * TP_DIM_B. There are TP_CASC_LEN * TP_SSR input B ports.

port <output> out [TP_SSR]

A window API of (TP_DIM_A / TP_SSR) * TP_DIM_B samples of a derived output type. There are TP_SSR output ports.

kernel m_MatmultKernels [TP_CASC_LEN *TP_SSR]

The array of kernels that will be created and mapped onto AIE tiles. There will be TP_SSR number of parallel cascade chains of length TP_CASC_LEN.

kernel untiler [TP_SSR]

The kernels that that will be created when output tiling is enabled ( TP_ADD_DETILING_OUT = 1 ) for each SSR *rank.

kernel tilerA [TP_CASC_LEN *TP_SSR]

The array of kernels that will be created when tiling on input A is enabled ( TP_ADD_TILING_A = 1 ). Kernels will pre-process and sent the data through cascade interface to corresponding: m_MatmultKernels .

kernel tilerB [TP_CASC_LEN *TP_SSR]

The array of kernels that will be created when tiling on input A is enabled ( TP_ADD_TILING_A = 1 ). Kernels will pre-process and sent the data through cascade interface to corresponding: m_MatmultKernels .