1.1.4 Example Output (Step 4) - 1.1.4 Example Output (Step 4) - 2025.2 English

Vitis Libraries

Release Date
2026-02-09
Version
2025.2 English
INFO: loading build_dir.hw.xilinx_u250_gen3x16_xdma_4_1_202210_1/data/app.bin of size 73728
INFO: loaded 73728 bytes from build_dir.hw.xilinx_u250_gen3x16_xdma_4_1_202210_1/data/app.bin
Found Platform
Platform Name: Xilinx
INFO: device name is: xilinx_u250_gen3x16_xdma_shell_4_1
INFO: Importing build_dir.hw.xilinx_u250_gen3x16_xdma_4_1_202210_1/blas.xclbin
Loading: 'build_dir.hw.xilinx_u250_gen3x16_xdma_4_1_202210_1/blas.xclbin'
INFO: created kernels
loadXclbin  7144.720789 msec
create kernels  158.030839 msec
create buffers  0.120546 msec
INFO: transferred data to kernel 0
copy to kernels  146.851691 msec
INFO: Executed kernel 0
call kernels  0.098555 msec
INFO: Transferred data from kernel0
copyFromFpga  0.457479 msec
total  7450.297623 msec
subtotalFpga  305.583425 msec

###########  Op Gemm  ###########
  C = postScale(A * B + X) 64x64 = 64x64 * 64x64 + 64 x 64
  Comparing ...
  Compared 4096 values:  exact match 1281  within tolerance 2815  mismatch 0
Gemm C Matches

test_result:pass