The AMD Vitis™ digital signal processing IP library (DSPIPLib) provides an implementation of different L1/L2/L3 elements for digital signal processing.
The DSPIPLib contains:
AI Engine DSP IP Library
The AMD Vitis AI Engine DSP IP library consists of designs of various DSP algorithms, optimized to take full advantage of the processing power of AMD Versal™ Adaptive SoC devices, which contain an array of AI Engines high-performance vector processors.
The library is organized into three parts:
- L1 AI Engine kernels
- L2 AI Engine graphs and VSS Makefiles
- L3 software APIs
Currently, there are no L3 software APIs. The recommended entry point for all library elements is an L2 graph for designs that include only AI Engines and a vss Makefile for designs including both AI Engine and PL components.
For more information, refer to Introduction for AIE DSP IP library.
The Vitis AIE DSP IP Library includes a VSS form of a Fast Fourier transform (FFT), and Finite Impulse Response (FIR) filters. For a full list of available DSP functions, refer to DSP Library Functions.
Note
The VSS FFT/iFFT solution in the Vitis DSP IP Library requires the FFT/IFFT implementation from the Vitis Library. See Vitis DSP Library documentation for more details.
Note
The VSS FFT/iFFT solution in the Vitis DSP IP Library may use components in the Vivado IP suite in addition to the FFT/IFFT implementation from the Vitis Library.
Introduction
L2 AIE DSP Library User Guide
API Reference