Vitis Tutorials: Platform Creation (XD101) - 2024.1 English

Vitis Tutorials: Platform Creation (XD101)

Document ID
XD101
Release Date
2024-06-19
Version
2024.1 English

What is a Platform?

Briefly speaking, a platform is a package that contains the HPFM (.xsa) file and SPFM (software components). When you input the .xsa file and software components, the AMD Vitis™ IDE tool will package them together and generate a platform .xpfm file, while the .xsa file is designed and exported from the AMD Vivado™ tool. Software components are prepared by AMD and ready to use for evaluation. Software components customization is also supported with Petalinux, if needed.

Platform Creation Example Quick Access

Platform Creation Tutorials

The tutorials under the Vitis Platform Creation category help you learn how to develop an extensible platform for your own board, or customize the Vitis platform on Xilinx demo boards.

  • The Design Tutorials showcase end-to-end workflow for creating the Vitis extensible platforms from scratch for different device families and boards.

  • The Feature Tutorials highlight specific features and flows that help develop the platform.

Design Tutorials

Tutorial

Device Family

Board

Platform Type

IDE Flow

Design Target

Vitis Platform Quick Start

Versal AI Core

VCK190

Flat

  • Vivado

  • Vitis Unified IDE

Highlights: Simplest Vitis Platform creation and usage flow.

  • Hardware design: Using Vivado Customizable Example Design template to quick start.

  • Software design: Using createdts and Common Image to quick start.

  • Verification: Vector Addition.

Note

This design flow is applicable to most AMD demo boards.

Create a Vitis Platform for Custom Versal Boards

Versal AI Core

VCK190

Flat

  • Vivado

  • Vitis IDE

Highlights: Platform design flow for custom boards.

  • Hardware design: Using Vivado Customizable Example Design (device part based) to create the hardware and do further customizations.

  • Software design: Using createdts and Common Image to quick start.

  • Verification: Vector Addition.

Note

This tutorial uses VCK190 board as a custom board. The design does not use any of its presets.

Versal DFX Platform Creation Tutorial

Versal AI Core

VCK190

DFX

  • Vivado

  • Vitis IDE

Highlights: Design flow for Vitis DFX (Dynamic Function eXchange) Platform.

  • Hardware design: Using Vivado Customizable Example Design template to quick start.

  • Software design: Using createdts and Common Image to quick start.

  • Verification: Vector Addition.

Create Vitis Platforms for Zynq UltraScale+ MPSoC

Zynq UltraScale+ MPSoC

ZCU104

Flat

  • Vivado

  • Vitis IDE

Highlights: Creating a Vitis platform for Zynq UltraScale+ MPSoC from scratch.

  • Hardware design: Creating the hardware design from scratch without any help from Vivado example design templates.

  • Software design: Using createdts and Common Image to quick start.

  • Verification: Vector Addition and Vitis-AI.

Custom Kria SOM Platform Creation Example

Zynq UltraScale+ MPSoC

KV260

Flat

  • Vivado

  • Vitis IDE

Highlights: Kria SOM Platform creation and usage flow.

  • Hardware design: Creating from scratch.

  • Software design: Using Common Image and showing device tree binary overlay (DTBO) creation flow.

  • Verification: Vector Addition and Kria SOM application loading procedure.

Feature Tutorials

Tutorial

Device Family

Board

Platform Type

IDE Flow

Design Target

Incorporating Stream Interfaces

Generic, but using Versal AI Core as example

VCK190

Flat

  • Vivado

  • Vitis IDE

Highlights:

  • Adding custom IP into the platform hardware.

  • Using AXI Stream IP in platform and kernel.

PetaLinux Building and System Customization

Zynq UltraScale+ MPSoC and Versal AI Core

ZCU104 and VCK190

Flat

  • Vivado

  • Vitis IDE

Highlights: Customize the software components with PetaLinux.

Hardware Design Fast Iteration with Vitis Export to Vivado

Versal AI Core

VCK190

Block Design Container

  • Vivado

  • Vitis IDE

Highlights:

  • Skip creating the platform before v++ linking.

  • Using Vivado to do design implementation and timing closure.

  • Fast iteration for hardware design.

Hardware Design Validation

Versal AI Core

VCK190

Flat & Block Design Container

  • Vivado

  • Vitis IDE

Highlights:

  • Link kernel with XSA directly.

  • Validation against hardware platform interfaces.

  • Validate the hardware design with bare-metal application.

XSA

Vivado exported archive file that contains hardware information required for Vitis and PetaLinux

DFX

Dynamic Function eXchange

SOM

System-on-Modules

DTB

Device Tree Binary

DTBO

Device Tree Binary Overlay