Step 5-2: Use Case 2: Vivado design changes that require PLIO interface change - 2024.1 English

Vitis Tutorials: Platform Creation (XD101)

Document ID
XD101
Release Date
2024-06-19
Version
2024.1 English

This step covers use-case 2 i.e. Vivado design changes affecting the PLIO interface. To import the latest VMA from Vitis, you have to remove the existing VMA from the Vivado project. To remove the imported VMA from the Vivado design, you can use one of the following two commands:

  1. vitis::remove_archive_hierarchy : This command can be used to remove the imported VMA BDC (VitisRegion.bd) only and keep the design modifications done in Vivado are intact. This command keeps internal links of Vitis Metadata which is helpful for the further hardware design interations.

  2. vitis::remove_archive : This command can be used to remove imported VMA BDC and all the bd variants generated after the vma import. This command is helpful in the scenarios where developer wants to clean the project with previous vma iterations and start with fresh vma import. It removes all internal links of Vitis Metadata and Vivado design modifications done in child bds.

For design development in iterations, it is recommended to use vitis::remove_archive_hierarchy.

In this tutorial, we are adding one HLS kernel (Polar_clip) in cascade to existing polar_clip kernel to show how to add another HLS kernel and modify the connectivity graph. Since we have already compiled the hls kernel and not done any change in the Vivado design, we need to only update the system.cfg. Updating the connectivity graph helps to establish the connection between polar-clip 1 to polar-clip 2. Following steps would help us to understand the flow:

  1. To remove the imported VMA only, using the Tcl API, vitis::remove_archive_hierarchy as shared above. image

The updated BD can be seen in the following image, only the VMA is removed and connections gets open for AIE and RTL-IPs.

image

  1. Modify the system.cfg to update the connectivity graph changes.

[connectivity]
nk=polar_clip:2:polar_clip_1.polar_clip_2
# Connect AIE input of PLIO-1 to RTL-IP port AIE_IN
stream_connect=AIE_IN:ai_engine_0.DataIn1
# Connect AIE output of PLIO-1 to input of HLS kernel: polar_clip_1
stream_connect=ai_engine_0.polar_clip_out:polar_clip_1.in_sample
# Connect output of polar_clip_1 to input of polar_clip_2
stream_connect=polar_clip_1.out_sample:polar_clip_2.in_sample
# Connect output of polar_clip_2 to input of AIE PLIO-2
stream_connect=polar_clip_2.out_sample:ai_engine_0.polar_clip_in
# Connect output of PLIO-2 to RTL-IP port AIE_OUT
stream_connect=ai_engine_0.DataOut1:AIE_OUT
  1. Run v++ –link to export .vma with modified system.cfg generated in step 2.

  2. Import the updated .vma into the Vivado project

image

In case if you want to make modifications in the Vivado design, you can do that in the following way:

  1. Make changes in the vck190_prj.bd (changes related to CIPS) or in the latest imported _vma.bd (changes related to PLIO interface).

  2. Validate and save the bd.

  3. Regenerate the target and re export the extensible XSA using the command ‘write_hw_platform -force <vck190_prj_ext_hw_1.xsa>’.

  4. This extensible XSA will have the Vivado design changes which are done after importing the previous VMA.

  5. Use the latest exported extensible XSA (vck190_prj_ext_hw_1.xsa) to re generate the VMA using following steps:

    5.1: If the changes are made related to AIE design or AIE-PL boundary, regenerate the libadf.a (remove old libadf.a or revision control it) with the newer extensible xsa.

    5.2: If the changes are made in the HLS kernels, re-compile the kernels with the newer extensible xsa to generate updated xos (remove old generated xos or revision control).

    5.3: Make the changes in the system.cfg file (as done in this use-case), reexport the VMA with updated libadf.a, xos, system.cfg and extensbile xsa. Repeat “Step-3” to import the modified VMA in the design.