Step 2 Create the software components in Vitis - 2024.1 English

Vitis Tutorials: Platform Creation (XD101)

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2024.1 English

After exporting the XSA, compile AIE and PL kernels to generate libadf.a and .xo file respectively.

Step 2.1: Compile the AIE Graph to generate libadf.a

Use the make command to generate the libadf.a (AIE compiled output).

make adf

The above make command compiles the graph.cpp using the v++ command: v++ -c –mode aie –platform ../hw/build/my_project/vck190_prj_ext_hw.xsa graph.cpp If you want to run the command directly from the terminal, you can run it from the AIE folder.

The graph has two PLIOs. The first PLIO is connected to interpolator AIE Kernel and the second PLIO is connected to classifier AIE Kernel.

Output: The generated libadf.a is located in the directory aie/libadf.a.

Step 2.2: Compile PL Kernels to generate the .xo File

We are using one PL kernels: polar clip. In this step, we compile the HLS kernel and generate the .xo file.

Make command to compile and generate .xo file:

make xos

The above make command compiles the polar_clip.cpp using the v++ command inside the pl_kernel folder:

v++ -c -k polar_clip -f ../hw/build/my_project/vck190_prj_ext_hw.xsa -s polar_clip.cpp -o polar_clip.xo

If you want to run the command directly from the terminal, you can run it from the pl_kernel folder.

Output: The generated .xo files are located in the directory pl_kernels/polar_clip.xo.

Step 2.3: Integrate the AIE+PL subsystem by linking the extensible platform (vitis_design_ext_hw.xsa), AIE graph (libadf.a), PL kernel (polar_clip.xo) and the Vitis configuration file (system.cfg). Use the –export_archive linker option to generate a Vitis Metadata Archive (vma) file which can then be imported in Vivado.

Use the make command to generate .vma file:

make vma

The above make command runs the the v++ -l command:

v++ -l –platform ../hw/build/my_project/vck190_prj_ext_hw.xsa ../pl_kernels/polar_clip.xo ../aie/libadf.a –save-temps –export_archive –config system.cfg -o vitis_design_hw.vma

In the configuration file (system.cfg), provide details about the connectivity between the AIE and PL IPs. Vitis uses the file to make the connectivity during linking:

# Connect AIE input of PLIO-1 to RTL-IP port AIE_IN
# Connect AIE output of PLIO-1 to input of HLS kernel: polar_clip_1
# Connect output of polar_clip_1 to input of AIE PLIO-2
# Connect output of PLIO-2 to RTL-IP port AIE_OUT

Output: The generated .vma file is located in vitis_impl/vitis_design_hw.vma.