Step 2: Add Custom IP into the Block Design - 2024.2 English - XD101

In this step, you add a DDS compiler IP into the platform design that you created in the last step. The DDS compiler IP is provided in the AMD IP catalog in the Vivado Design Suite. For more details, see PG141. Because it is a publicly available IP, it supports simulation inherently. If you want to add your own IP cores, you must provide simulation models to support simulation.

1. Reopen the system block design that was created in last step if you have already closed it.

2. Click the Add IP (plus icon) button and search for dds. Double click the DDS compiler IP to add it to the canvas.

   

3. Configure the DDS IP as follows. Be aware that some of the settings are not a hard requirement and are just for the purpose of this design. The only hard requirement is that there is only a single AXI4-Stream interface for this IP and therefore the phase output port is disabled.

   a. Configuration Tab Settings:

   

   b. Implementation Tab Settings:

   

   c. Detailed Implementation Tab Settings:

   Keep the default settings for this page.

   d. Output Frequency Tab Settings:

   You can adjust the frequency value but keep the sample rate in mind. The clocking rate is 300 MHz. If there are too few samples within one cycle, the sine wave cannot be sampled correctly.

   

4. Exit the configuration page and connect the aclk port to the clk_out1 signal of clocking wizard.

5. Now the block design should look like the following:

1. Open up platform setup window and enable the M_AXIS_DATA port. Set the SP Tag to AXIS - this will be used by the Vitis™ linker to connect to the accelerator.

1. Regenerate the block design output products.

2. Export the hardware platform. In the platform type selection page, choose Hardware and hardware emulation to run emulation with this platform.