Step 1 : Create the hardware design in Vivado - 2024.1 English

Vitis Tutorials: Platform Creation (XD101)

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2024.1 English

Step 1.1 : Creating a BDC based hardware design in Vivado using the Tcl flow. The Tcl files are shared in directory hw/xsa_scripts. If you want to use the flow on non-BDC design, you need to convert the non-BDC design to BDC design. Refer the link to convert non-BDC design to BDC design.

To run the complete hardware flow for this tuotiral, use the make command:

make all TARGET=hw

Below steps help you to go through the flow step by step:

Use the following make command to generate the Vivado project through Tcl:

make xsa

The above make command source the xsa.tcl (top file) file. The tcl file calls below files:

 1. project.tcl : Creates the project my_project in Vivado for the board VCK190 and create the BDC (Block Design Container) as ext_bdc. 

 2. ext_bdc.tcl : Create the block design ext_bdc.tcl. In this BDC, AIE and related PL IPs are placed and connections are done through the tcl. 

 3. vck190_bd.tcl : Create the and configures CIPS, CIPS NoC and Memory controllers for DDR4 and LPDDR4 and make connections. 

 4. pfm_decls.tcl : Set the platform attributes for the ext_bdc design like SP TAGs for AXI Port, clock, interrupt etc. 

Open the Vivado project by opening the project file .xpr from the path: ./hw/build/my_project folder/my_project.xpr


Step 1.2: Add the custom RTL IPs in Vivado. Here, we are using stream_in and stream_out RTL IPs which we are adding in Stream_out RTL IP is a free running RTL block which generates the stream data indefinitely. Stream_in IP receives the data from AIE and status of the received data can be checked by PS through AXI Lite interface. Below steps demonstrates how to add custom RTL IPs in the bd to export the extensible xsa from the Vivado. This step can also be done by sourcing “my_project_changes.tcl” located in hw folder or by using the make command make viv_changes.

  1. Package RTL IPs. (We have placed the packaged RTL IPs in the folder custom_ip)

  2. Add the RTL path in the IP repository from the project manager settings in the Vivado. After adding the path click ok.


  1. Open



a. Change IP configuration settings for following IPs:

	a. icn_ctrl: Set the master ports to 7. 

	b. DDRNoC : Set the slave axi ports to 0. 

	c. LPDDRNoC : Set the slave axi ports to 0.

b. Connecting the clock of both RTL-IPs to clock_out1, reset_n to reset generated by clk_out1 and connect stream_in slave AXI port to Master port 7 of icn_ctrl.


c. Assign the address to the port: /stream_in_/s_axi_ontrol.

  1. Go to Platform setup: Select AXI Stream Port: Give the SPTAG name to stream port of stream_out as AIE_IN and stream_in as AIE_OUT. image

  2. Validate and save the bd : ext_bdc. Ignore the warning as we are going to connect the intr port of axi_intc_cascaded_1, stream port of stream_in_0 and stream port out_r of stream_out_0 during the v++ –link in step 2.3