The recommended steps are as follows:
Develop hardware design in Vivado.
Export the extensible platform (.xsa) from Vivado.
Use the Extensible platform (.xsa) in Vitis to develop and compile AI Engine Graph application and PL kernels.
Link the AIE / PL compiled output, connectivity graph, extensible platform to export the VMA (Vitis Metadata Archive) in Vitis.
Import the VMA file into Vivado.
To run the design in hardware emulation:
6.1: Run simulation scripts
6.2: Generate fixed xsa in Vivado
6.3: Run v++ package target hw_emu to generate xclbin in Vitis
6.4: Run host.exe
To run the design in hardware:
7.1: Run synthesis and implementation. Close timing in Vivado.
7.2: Generate fixed.xsa in vivado
7.3: Run v++ package target hw to generate xclbin in Vitis
7.4: Take the design to hardware and run host.exe
The steps in the above diagram are covered in detail in the below section “Design Flow”.
The Vitis export to the Vivado flow introduces a new v++ link option and three new Tcl APIs. This tutorial helps you understand how to use this flow:
The v++ link option introduced in this flow to generate Vitis Metadata is:
v++ -l --export_archive
This option can be used with v++ –l only. Do not use –target with this command, it is not supported.
The Vivado Tcl APIs are introduced in this flow to import and remove the VMA from Vivado are:
vitis:: import_archive
vitis:: remove_archive_hierarchy
vitis:: remove_archive