Modifying the linker configuration - 2025.1 English - XD101

Vitis Tutorials: Platform Creation (XD101)
Document ID
XD101
Release Date
2025-07-31
Version
2025.1 English

Start with inspecting the VSS and Vitis linker configurations.

VSS configuration Vitis configuration
vss/src/vss_conn.cfg vitis/src/system.cfg

Then edit the vitis/src/system.cfg and do the following changes:

  1. Add all statements from vss_conn.cfg, except the line with vss= declaration.

  2. Cut any vss_top_ from concatenate names.

  3. Remove any redundant statements, such as freqhz for counter_0.

The result should look like this:

#
# Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

# From VSS
# Reduntant -- Remove this line --> freqhz=500000000:counter_0
freqhz=250000000:axis1to2_0,vadd_s_0
# From Vitis
freqhz=500000000:subtractor_0.aclk,counter_0
freqhz=250000000:mm2s_1,s2mm_1,subtractor_0.s00_axi_aclk

[connectivity]
# Added from VSS:
nk=counter:1:counter_0
nk=vadd_s:1:vadd_s_0
nk=axis1to2:1:axis1to2_0

# From Vitis
nk=subtractor:1:subtractor_0
nk=mm2s:1
nk=s2mm:1

# Added from VSS:
# Not needed -- Remove this line --> vss=amd.com:my_vsslib:vss_top:1.0:counter_0,vadd_s_0,axis1to2_0,ai_engine_0
sc=counter_0.m01_axis:ai_engine_0.dm_in0
# to add fifo, add :<fifo_depth> to connection
#sc=counter_0.m02_axis:ai_engine_0.dm_in1:16
sc=counter_0.m02_axis:ai_engine_0.dm_in1
sc=counter_0.m03_axis:ai_engine_0.dm_in2
sc=counter_0.m04_axis:ai_engine_0.dm_in3
sc=axis1to2_0.out0:ai_engine_0.fir_sig_in0
sc=axis1to2_0.out1:ai_engine_0.fir_sig_in1
sc=ai_engine_0.fir_sig_out0:vadd_s_0.in0
sc=ai_engine_0.fir_sig_out1:vadd_s_0.in1

# From Vitis
# Connect counter output channels to subtractor, routing two of them through AIE data mover kernels
sc=counter_0.m00_axis:subtractor_0.s00_axis
sc=ai_engine_0.dm_out0:subtractor_0.s01_axis
sc=ai_engine_0.dm_out1:subtractor_0.s02_axis
sc=ai_engine_0.dm_out2:subtractor_0.s03_axis
sc=ai_engine_0.dm_out3:subtractor_0.s04_axis

# Connect mm2s to feed an axis 1 to 2 stream duplicator to feed the AIE FIR filters
sc=mm2s_1.s:axis1to2_0.in0
# Connect the vadd_s from vss_top to s2mm so the output data can be analyzed with PS
sc=vadd_s_0.out0:s2mm_1.s

sp=mm2s_1.mem:DDR
sp=s2mm_1.mem:DDR

[clock]
#id=0 -> clk_out1_o1 -> 500.00MHz
#id=0:subtractor_0,counter_0

#id=1 -> clk_out1_o2 -> 250.00MHz
#id=1:vadd_mm_1

#id=2 -> clk_out1_o3 -> 125.00MHz

#id=3 -> clk_out1_o4 -> 62.50MHz

#id=4 -> clk_out2 -> 333.33MHz
#id=4:vadd_s_1,mm2s_vadd_s_1,mm2s_vadd_s_2,s2mm_vadd_s_1

[advanced]
#param=hw_emu.enableProfiling=false
#param=compiler.addOutputTypes=hw_export

[vivado]
param=project.enableUnifiedAIEFlow=true

A cleaned up example for the Vitis linker configuration is provided here: vitis/src/system.cfg.