Vitis Tutorials: Hardware Acceleration (XD099) - 2024.2 English

Document ID: XD099
Release Date: 2024-12-13
Version: 2024.2 English

Vitis Tutorials: Hardware Acceleration (XD099)
Feature Tutorials
Getting Started with RTL Kernels
Tutorial Overview
Before You Begin
Accessing the Tutorial Reference Files
Vector-Accumulate RTL IP
Next Steps
Mixing C and RTL
Introduction
Tutorial Overview
Before You Begin
Accessing the Tutorial Reference Files
Step 1: Building an Application with C++ Based Kernel
C++ Based Kernel
Host Code
Build the Application
Run Emulation
Review the Application Timeline
Putting it All Together
Step 2: Building an Application with C++ and RTL-Based Kernels
Host Code Updates
Build and Emulation with C++ and RTL Based Kernels
Next Steps
Dataflow Debug and Optimization
Introduction
Accessing the Tutorial Reference Files
Next Steps
Using Multiple DDR Banks
Introduction
Tutorial Overview
Before You Begin
Accessing the Tutorial Reference Files
Tutorial Setup
Set v++ Linker Options
Conclusion
Using Multiple Compute Units
Introduction
Tutorial Overview
Before You Begin
Accessing the Tutorial Reference Files
Makefile Flow
Run Hardware Emulation
Inspect the Host Code
Emulation Result
Improve the Host Code for Concurrent Kernel Enqueuing
Increasing the Number of CUs
Run Hardware Emulation and Inspect the Change
Conclusion
Controlling Vivado Implementation
Introduction
Tutorial Overview
Before You Begin
Accessing the Tutorial Reference Files
Set Up the Vitis Environment
Controlling Vivado Synthesis and Implementation through the Vitis Compiler
Optimizing the Design in the Vivado Tool
Reuse the Optimized Checkpoint to Create the Device Binary
Putting it All Together
Conclusion
Optimizing for HBM
Introduction
Before You Begin
Accessing the Tutorial Reference files
Generating all the xclbins
Tutorial Overview
Host Memory Access
XRT and Platform version
Tutorial Description
Kernel structure
Host code
Kernel compilation
Running the application
Summary
Using GT Kernels and Ethernet IPs on Alveo
Features and Design Overview
Design Flow and Tutorial Steps
1. Generate the IP
2. Package Kernels
3. Vitis Linking
Summary
Enabling FPGA to FPGA P2P Transfer
XRT and Platform Version
Introduction
Step 1: Understanding the Original (non-p2p) Version of the Host Code
2. Running an Original (non-p2p) Version of the Design
3. Understanding the Changes Required for p2p Transfer
Steps required for p2p Data Transfer
4. Running the p2p Version of the Design
Appendix: Understanding and review7ing the Design to Reverse the Dataflow Direction with the Same Setup
Support
Design Tutorials
Bloom Filter Example
Introduction
Before You Begin
Accessing the Tutorial Reference Files
Tutorial Outline
Convolution Example
Introduction to Acceleration
Cloning the GitHub Repository and Setting Up the Vitis Tool
Clone Git Repo
Copy and Extract Large Files
Setting Up the Vitis Tool
Baseline the Application Performance
Running FPGA Accelerated Application
Launching the Host Application
Results
RTL Systems Integration Example
RTL Kernel: rtc_gen (XO)
HLS C Kernel: alpha_mix (XO)
HLS C Kernel: strm_dump (XO)
Bitstream Implementation (XCLBIN)
rtc_gen_test_hw.xclbin / rtc_gen_test_hw_emu.xclbin
rtc_alpha_hw.xclbin / rtc_alpha_hw_emu.xclbin
Test Program
rtc_gen_test.cpp
rtc_alpha_tb.cpp
How to Use This Repository
Build the hardware
Build and Run the Software
Step 1: Generate the Makefile
Step 2: Compile the Programs
Step 3: Configure the Running Mode (Hardware or Hardware Emulation)
Run in Hardware Mode
Run in Hardware Emulation Mode
Step 4: Run the Executables rtc_gen_test or rtc_gen_test_emu
Step 5: Run the executables rtc_alpha_tb or rtc_alpha_tb_emu
Step 6: Try the Vitis Profiling Function with rtc_gen_test and rtc_alpha_tb Program
Traveling Salesperson Problem
Introduction
Run a Simple CPU Implementation
Set Up Vitis
Set Up the Environment to Run Vitis
Accessing the Tutorial Files
Next Steps
Bottom RTL Kernel Design Flow Example
About This Tutorial
Device and Software Requirements
Additional Requirements for RedHat/CentOS
Additional Requirements for Ubuntu
Tutorial Contents
Choleskey Algorithm Acceleration
XRT Host Code Optimization
Introduction
Tutorial Overview
Before You Begin
Accessing the Tutorial Reference Files
Model
Building the Device Binary (xclbin)
Host Code
host.cpp Main Functions
Lab 1: Pipelined Kernel Execution Using Out-of-Order Event Queue
Lab 2: Kernel and Host Code Synchronization
Lab 3: OpenCL API Buffer Size
Conclusion
Next Steps
Aurora Kernel on Alveo
Introduction
Develop krnl_aurora kernel
Generate Aurora 64B/66B Core IP
Generate AXI Stream Data FIFO IP
AXI Control Slave Module
krnl_aurora Top Module
Package krnl_aurora Kernel
strm_issue and strm_dump Kernel
Kernel Integration (Linking)
Host Program
One More Thing
1. About Aurora IP
2. RTL Kernel krnl_aurora
3. HLS Kernel strm_issue and strm_dump
4. Top-level Linking Consideration
Summary
Revision History
Single Source Shortest Path Application
Single Source Shortest Path Application with Vitis Libraries for Acceleration
Problem Description
About This Tutorial
Tutorial Structure
Summary
Reference
Get Moving with Alveo
Introduction
Provided Design Files
Build the Software and Hardware

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