Once synthesis completes, review the updated report to verify improvements and identify any remaining loops or functions that do not meet the performance target.
The report indicates that a shift loop inside the update_window loop still requires further optimization. The main issue is that this critical shift loop takes 13 clock cycles per shift, whereas the ideal target is 1 cycle per shift. This inefficiency is a major contributor to the performance bottleneck.
To address this:
Right-click Goto Source in the report to navigate directly to the loop in
filter2d_hw.cpp.Apply the following pragma to the shift loop:
#pragma HLS performance target_ti = 1
Re-run C Synthesis and check the updated report to confirm that the performance target is met. The updated synthesis report shows that the entire design now meets the performance targets. By applying targeted loop-level pragmas and iterating through synthesis, we eliminated the critical bottlenecks and achieved the desired throughput for the 2D convolution. This confirms that our optimization strategy was effective and the design is ready for the next stage.
Target: 2,142,857 cycles/frame
Achieved: 2,087,068 cycles/frame