Results - 2025.1 English - XD261

In this section, we will use Vitis to create an HLS Component with the .cpp files (mgs_qrd_wbs.cpp and mgs_qrd_wbs_tb.cpp), and then synthesize and compare the reuslts on a Zynq™ Ultrascale+™ RFSoC and a Versal™ Premium series adaptive SoC.

1. Open the Vitis Unified IDE and specify a new or existing workspace.

2. Create a new HLS Component by clicking Create Component under HLS Development in the Welcome Screen.

3. Name the component mgs_qrd_wbs_usplus

4. In the Source Files step, add the file ./reference_files/mgs_qrd_wbs.cpp as a Design File, add the file ./reference_files/mgs_qrd_wbs_tb.cpp as a Test Bench File, set the Top Function to mgs_qrd, and press Next.

5. Either Browse to or type in xczu28dr-ffve1156-1L-i, press next, set the clock target to 3ns, then finish the Wizard.

6. Run and verify the results of C Simulation by pressing Run under C SIMULATION in the FLOW panel. The output should resemble the following:

    INFO: [SIM 211-1] CSim done with 0 errors.
    INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 2 seconds. Elapsed time: 83.491 seconds; current allocated memory: 1.836 MB.
    INFO: [HLS 200-1510] Running: close_project 
    INFO: [HLS 200-112] Total CPU user time: 3 seconds. Total CPU system time: 5 seconds. Total elapsed time: 89.947 seconds; peak allocated memory: 192.961 MB.
    INFO: [Common 17-206] Exiting vitis_hls at Thu Dec 14 11:29:08 2023...
    INFO: [vitis-run 60-791] Total elapsed time: 0h 1m 37s
    C-simulation finished successfully
   

7. Run C Synthesis and open the Synthesis Report.

   

   Now, we want to create a new HLS Component so we can analyze the results of the design on a Versal Premium series device without touching our existing results.

8. Right-click component mgs_qrd_wbs_usplus in the VITIS COMPONENTS panel and select Clone Component. Name the new component mgs_qrd_wbs_versal

9. Select mgs_qrd_wbs_versal in the Component dropdown of the FLOW panel.

10. Click the gear to the right of the component selection drop-down.

11. Select hls_config.cfg

12. Under ‘General’, go to ‘part’, and either Browse to or type in vp1202-vsva2785-1LP-i-L

13. Run C Synthesis and view the Synthesis Report

The results from Vitis HLS C Synthesis targeting the Zynq Ultrascale+ device and Versal Premium device are summarized in Table 1. This design is an MGS QRD+WBS core targeting a matrix of 32 rows and 32 columns. However, the design is flexible such that it can support variable rows up to 128 and variable columns up to 64.

Table 1:

	Zynq Ultrascale+	Versal Premium
MAX CLOCK (MHZ)	317	342
LATENCY (CYCLES)	742186	231498
INTERVAL (CYCLES)	742187	231499
BRAM	128	128
DSP	219	257
FF	355711	321193
LUT	131661	318777
URAM	0	0

The table shows that with a comparable amount of resources, the Versal Premium device was able to greatly increase performance by two key factors. First, the Versal Premium device was able to achieve a 7.9% greater maximum clock. In addition, throughput of the design, as measured by cycles, was improved by over 3X. A key reason for this improvement is due to the more efficient DSP58 primitive on the Versal Premium device compared to the DSP48 primitive on the Zynq Ultrascale+ device. In the native floating-point mode, the DSP58 can compute a floating point multiply accumulate with just one DSP primitive, compared to the emulated DSP48 floating-point arithmetic provided by the parts in the Ultrascale+ family.