Performance Pragma Overview - Performance Pragma Overview - 2026.1 English - XD261

Vitis Tutorials: Vitis HLS (XD261)

Document_ID
XD261
Release_Date
2026-07-20
Version
2026.1 English

Performance Pragma introduces a top-down optimization flow that starts with defining a global performance target rather than focusing on individual loops. The methodology includes:

flowchart TD
    A["Define Throughput Goal (target_ti)"] --> B["Re-architect for Dataflow (Load → Compute → Store)"]
    B --> C["Profile Loop Trip Counts via C-sim (optional manual refinement)"]
    C --> D["Apply Performance Pragmas (Top-level & Loop-level)"]
    D --> E["Iterate and Validate (Check synthesis report)"]
    E -->|Refine pragmas| D

For more details on pragma syntax and methodology, see UG1399.