Optimize the design by Pipelining and Unrolling loops - 2025.1 English - XD261

Vitis Tutorials: Vitis HLS (XD261)
Document ID
XD261
Release Date
2025-06-17
Version
2025.1 English

Before optimizing any IP, one should start with a design goal. In the case of this Beamformer IP, the design goal is to process the Pulse Repetition Interval (PRI) of 2500 samples within 9 us. At a 3 ns clock period, or approximately 333.3 Mhz, that calculates to a maximum interval of 3000 clock cycles. If we look at the loop bounds of loop L1 in the code, we can see that it iterates from int i = 0 to i = SAMPLES, and SAMPLES is defined in the header as 2500. Because the function must have an interval of less than or equal to 3000 clock cycles, we know that the loop must also have an interval of less than 3000 clock cycles. With 2500 iterations, we know that if each iteration takes 2 clock cycles, the loop interval will take at minimum 5000 iterations. Thus, in this loop, we know that each iteration must be able to execute in the very next clock cycle after the previous iteration. This metric is called the Initiation Interval, or II: the measure of the number of clock cycles in between successive iterations of the loop So, our strategy for achieving the specified performance will be to apply a PIPELINE II=1 pragma to loop L1 and then ensure the HLS C Synthesizer is able to meet the requested II.

  1. In the HLS DIRECTIVE Panel, select loop L1, and press +. In the drop-down, choose the PIPELINE pragma. Switch the pragma location to Config File, and set II to 1. Click OK.

  2. Run C Synthesis again and open the Synthesis Report. Expand the Performance and Resource Estimates section.

    First, note that only one level of loop hierarchy exists. When a PIPELINE directive is used, Vitis HLS will infer an UNROLL directive on all loops within that loop scope. This is necessary to achieve the requested initiation interval. Second, notice that there is a new column called “ISSUE TYPE”. In loop L1, the level where the Pipeline target II of 1 was applied, there is an issue labeled “II Violation”, with a “Timing Violation” in the level above. We can use analysis tools to help guide us on the next steps for resolving these issues.

    Synthesis Report showing II Violation and Timing Violation on Loop L1

  3. Right-click on the II violation, and then select Go To II Violation.

This will bring you to the II Violation view of the Schedule Viewer. This view shows us a series of loads that were scheduled on the variable rx_q:

Schedule Viewer showing II Violation on Variable rx_q

In order to achieve an II of 1, all 16 of these loads would need to occur in one clock cycle. Because they can’t, the II parameter is violated and the performance target cannot be achieved. In the next section, we learn more about this issue and how to resolve it.