Most radars today employ some type of adaptive digital beamforming. A high-level block overview of the receiver beamforming concept is illustrated in Figure 1.
As technical requirements increase, radar designs are expected to occupy progressively higher bandwidths, requiring receiving systems to become more reliable at suppressing the effects of noise sources, off-target antenna side-lobe content, interference from hostile jamming signals, and the “clutter” present within the wider pass-bands characteristic of the newer radar technologies. All this must be done while maintaining directional control of each antenna array element—individually and simultaneously, in real time. Successfully completing these tasks within given time limits is accomplished through element-level processing. Put simply, that means that the signal of each antenna element is received individually and processed simultaneously.
A critical part of element-level processing is adaptive digital beamforming. This white paper focuses on the technology of adaptive beamforming and how it can be implemented using AMD FPGAs and adaptive SoCs to create a beam-agile radar system at reduced cost, complexity, power consumption, and time to market than legacy solutions.
Using the technology and AMD components described in this white paper, a beam-agile radar can be created by calculating complex floating point adaptive weights. These weights are sampled from a previous pulse repetition interval (PRI). The challenge of calculating these weights is contained within the need to perform a complex matrix inversion that solves Equation 1 before the next PRI of data is received:
Equation 1:
Where:
\(A\) = the complex matrix, size $[m,n]$ where $m \geq n$ ; these are receive samples.
\(x\) = the complex vector being solved for, which becomes the adaptive weights, size $[n,1]$.
\(b\) = the desired response or steering vector, size $[m,1]$.
To solve for \(x\), one cannot divide \(b\) by \(A\). This is where the modified Gram-Schmidt (MGS) QR decomposition (QRD) is needed, which calculates the matrix inversion. The MGS QRD must use floating-point arithmetic to maintain the precision of the adaptive weight solution.
Solving for \(x\) in Equation 1 requires a deterministic, low-latency solution of matrix size that is a function of the radar system requirements. Traditionally, this arithmetic has been performed by numerous parallel CPUs to ensure that the floating-point calculations were completed before the next PRI. Given the size, weight, and power constraints of many radar systems, the CPU/GPU approach is not the best option to accomplish these calculations.
AMD FPGAs can perform highly parallel floating point arithmetic much more efficiently, using less hardware. The flexibility of AMD FPGAs allows the radar designer to consume vast amounts of data over flexible I/O standards such as JESD204B, SRIO, PCIe®, etc., then calculate the adaptive weights in one FPGA, in real time.