Vitis™ HLS ( High-Level Synthesis) enables developers to describe hardware using C/C++ and automatically generate RTL for FPGA implementation. This approach accelerates design cycles and improves productivity compared to traditional RTL coding. However, achieving performance goals in Vitis™ HLS has traditionally required inserting low-level pragmas, such as pipeline, unroll, and array_partition, to guide the compiler. This manual process can be iterative, time-consuming, and highly sensitive to design changes.
To address these challenges, Performance Pragma provides a higher-level optimization mechanism. Instead of tuning individual loops with multiple pragmas, designers can specify a system-wide throughput goal, and the compiler automatically infers and applies the necessary optimizations. This simplifies the workflow and makes performance tuning more intuitive.
The purpose of this tutorial is to demonstrate how to use Performance Pragma effectively through a practical example. We will walk through a 2D convolution design and show how to apply Performance Pragma step by step to meet a defined performance target. By the end, you will understand not only what Performance Pragma is, but also how to integrate it into your design flow for maximum benefit.
For detailed reference on Vitis HLS concepts and pragma syntax, see the UG1399.