Starting with Vitis HLS 2025.2, manual loop trip count annotation is no longer required. Instead, the tool can automatically capture loop iteration counts during C simulation.
Run C Simulation by clicking Run under C SIMULATION in the Flow navigation panel.
When the Run C SIMULATION Basic Settings window appears, enable the option
hls.csim.profile_tripcount, then click Run.The tool will profile loop iterations, generate a
csim.tclfile under Output > csim > profile, and use this data for accurate performance budgeting during C synthesis.