Users can use the get_pins API to get the pins in an XSA file. These can be pins at a high level
Vitis [0]: pins = HwDesign.get_pins(hierarchical='true')
Vitis [0]: print(pins)
'bram_addr_a','bram_addr_b','bram_clk_a','bram_clk_b','bram_en_a','bram_en_b','bram_rddata_a','bram_rddata_b','bram_rst_a','bram_rst_b','bram_we_a','bram_we_b','bram_wrdata_a','bram_wrdata_b','s_axi_aclk','s_axi_araddr','s_axi_arburst','s_axi_arcache','s_axi_aresetn','s_axi_arlen','s_axi_arlock'
Similar to the cells object previously, users can return the pin properties
Vitis [0]: pins[0].report_property()
Property Type Read-only Value
CLASS string true port
CLK_FREQ string true
DIRECTION string true O
INTERFACE bool true 1
IRQID string true
IS_CONNECTED bool true 1
LEFT string true 12
NAME string true bram_addr_a
POLARITY enum true
RIGHT string true 0
SENSITIVITY enum true
TYPE enum true undef
Users can use this to make a better filter. For example, if users wantred to return all clk pins
Vitis [0]: clk_pins = HwDesign.get_pins(hierarchical='true',filter='TYPE==clk')
Vitis [0]: print(clk_pins)
'bram_clk_a','bram_clk_b','s_axi_aclk','clka','clkb','s_axi_aclk','ACLK','M00_ACLK','M01_ACLK','S00_ACLK','S01_ACLK','slowest_sync_clk','maxihpm0_fpd_aclk','maxihpm1_fpd_aclk','pl_clk0'
Users can return the pins on a specfic object such as the axi_gpio cell used above
Vitis [0]: print(cells[0])
axi_bram_ctrl_0
Vitis [0]: axi_gpio_pins = HwDesign.get_pins(of_object=cells[0],filter='TYPE==clk')
Vitis [0]: print(axi_gpio_pins)
'bram_clk_a','bram_clk_b','s_axi_aclk'
Filtering on the TYPE pin property is also useful to find all interrupt pins
Vitis [0]: axi_gpio_pins = HwDesign.get_pins(of_object=cells[0],filter='TYPE==INTERRUPT')
Users can filter on the pin DIRECTION && TYPE
Vitis [0]: axi_gpio_in_clks = HwDesign.get_pins(of_object=cells[0],filter='DIRECTION==I&&TYPE==clk')
Vitis [0]: print(axi_gpio_in_clks)
s_axi_aclk