pragma HLS PIPELINE II=1 - 2025.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2025-08-25
Version
2025.1 English

The datamover kernel has a for loop that is a candidate for burst read because the memory addresses per loop iteration are consecutive (ARBURST=INCR). To pipeline this for loop, you can use this pragma by setting the initiation interval (II) = 1.

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