After compiling the AI Engine kernels, graph, and PL HLS kernels, you can link them with the platform. Use the Vitis compiler to generate an XSA file.
Vitis tools integrate the AI Engine, HLS, and RTL kernels into an existing extensible platform. This is an automated step from a software developer perspective. The hardware designer provides the chosen platform. Alternatively, you can use one of the many extensible base platforms provided by AMD. The Vitis tools can then build the hardware design and integrate the AI Engine and PL kernels.
To test this feature in this tutorial, use the base VCK190 platform to build the design. The following example shows the command to run this step (default TARGET=hw_emu, GEMM_INSTS=1, GEMM_SIZE=32, ITER_CNT=1 and EN_TRACE=0):
make xsa
The command along with the options used is as follows:
...
VPP_FLAGS := --platform $(PLATFORM)
VPP_FLAGS += --save-temps
VPP_FLAGS += --temp_dir $(BUILD_TARGET_DIR)/_x
VPP_FLAGS += --verbose
VPP_FLAGS += -g
...
VPP_LINK_FLAGS += --clock.freqHz $(VPP_CLOCK_FREQ):$(DATAMOVER_KERNEL_TOP)_0
VPP_LINK_FLAGS += --clock.defaultTolerance 0.001
### If Profiling for Performance Measurement is enabled..
ifeq ($(EN_TRACE),1)
ifeq ($(TARGET),hw)
VPP_LINK_FLAGS += --profile.data $(DATAMOVER_KERNEL_TOP):all:strmInp_from_C0
VPP_LINK_FLAGS += --profile.trace_memory DDR
endif
endif
VPP_LINK_FLAGS += --config $(SYSTEM_CONFIGS_REPO)/x$(GEMM_INSTS).cfg
VPP_LINK_FLAGS += --vivado.prop fileset.sim_1.xsim.simulate.log_all_signals=true
VPP_LINK_FLAGS += --vivado.prop run.impl_1.STEPS.PLACE_DESIGN.TCL.PRE=$(DIRECTIVES_REPO)/prohibit_select_bli_bels_for_hold.tcl
VPP_LINK_FLAGS += --vivado.prop run.synth_1.STEPS.SYNTH_DESIGN.ARGS.CONTROL_SET_OPT_THRESHOLD=16
VPP_LINK_FLAGS += --vivado.prop run.impl_1.{strategy}={Performance_ExplorePostRoutePhysOpt}
...
xsa: kernels graph $(BUILD_TARGET_DIR)/$(XSA)
$(BUILD_TARGET_DIR)/$(XSA):$(KERNEL_XOS) $(SYSTEM_CONFIGS_REPO)/*
cd $(BUILD_TARGET_DIR); \
v++ -l $(VPP_FLAGS) $(VPP_LINK_FLAGS) -t $(TARGET) -o $@ $(KERNEL_XOS) $(LIBADF_A)
Refer to this page for a detailed description of Vitis linking options.
Switch |
Description |
|---|---|
–platform | -f |
Specifies the name of a supported acceleration platform as specified by the $PLATFORM_REPO_PATHS environment variable or the full path to the platform XPFM file. |
–save-temps | -s |
Directs the V++ command to save intermediate files/directories created during the compilation and link process. Use the |
–temp_dir |
This lets you manage the location where the tool writes temporary files created during the build process. The Vitis compiler writes temporary results. Then it removes them unless you specify the |
–verbose |
Display verbose/debug information. |
–config <config_file> |
Specifies a configuration file containing V++ switches. |
–output | -o |
Specifies the name of the output file generated by the V++ command. In this design the outputs of the DMA HLS kernels and the PL kernels interfacing with the AI Engine are in XO files. |
–profile.data [<kernel_name>|all]:[<cu_name>|all]:[<interface_name>|all](:[counters|all]) |
Enables monitoring of data ports through the monitor IP cores. You must specify this option during linking. Refer to this page for detailed profiling options. |
–profile.trace_memory <FIFO>:<size>|<MEMORY>[<n>] |
When building the hardware target (-t=hw), use this option to specify the type and amount of memory to use for capturing trace data. Refer to this page for detailed profiling options. |
A configuration file, system_configs/x$(GEMM_INSTS).cfg, tells the linker how to connect the AI Engine and PL kernels together. The file describes the overall connection scheme of the system.
[connectivity]
nk=dma_hls:1:dma_hls_0
#Connections For GEMM Insts 0...
stream_connect=dma_hls_0.strmOut_to_A0:ai_engine_0.DataInA0_CASC0:512
stream_connect=dma_hls_0.strmOut_to_A1:ai_engine_0.DataInA0_CASC1:512
stream_connect=dma_hls_0.strmOut_to_A2:ai_engine_0.DataInA0_CASC2:512
stream_connect=dma_hls_0.strmOut_to_A3:ai_engine_0.DataInA0_CASC3:512
stream_connect=dma_hls_0.strmOut_to_A4:ai_engine_0.DataInA0_CASC4:512
stream_connect=dma_hls_0.strmOut_to_A5:ai_engine_0.DataInA0_CASC5:512
stream_connect=dma_hls_0.strmOut_to_A6:ai_engine_0.DataInA0_CASC6:512
stream_connect=dma_hls_0.strmOut_to_A7:ai_engine_0.DataInA0_CASC7:512
stream_connect=dma_hls_0.strmOut_to_B0:ai_engine_0.DataInB0_CASC0:512
stream_connect=dma_hls_0.strmOut_to_B1:ai_engine_0.DataInB0_CASC1:512
stream_connect=dma_hls_0.strmOut_to_B2:ai_engine_0.DataInB0_CASC2:512
stream_connect=dma_hls_0.strmOut_to_B3:ai_engine_0.DataInB0_CASC3:512
stream_connect=dma_hls_0.strmOut_to_B4:ai_engine_0.DataInB0_CASC4:512
stream_connect=dma_hls_0.strmOut_to_B5:ai_engine_0.DataInB0_CASC5:512
stream_connect=dma_hls_0.strmOut_to_B6:ai_engine_0.DataInB0_CASC6:512
stream_connect=dma_hls_0.strmOut_to_B7:ai_engine_0.DataInB0_CASC7:512
stream_connect=dma_hls_0.strmOut_to_B8:ai_engine_0.DataInB1_CASC0:512
stream_connect=dma_hls_0.strmOut_to_B9:ai_engine_0.DataInB1_CASC1:512
stream_connect=dma_hls_0.strmOut_to_B10:ai_engine_0.DataInB1_CASC2:512
stream_connect=dma_hls_0.strmOut_to_B11:ai_engine_0.DataInB1_CASC3:512
stream_connect=dma_hls_0.strmOut_to_B12:ai_engine_0.DataInB1_CASC4:512
stream_connect=dma_hls_0.strmOut_to_B13:ai_engine_0.DataInB1_CASC5:512
stream_connect=dma_hls_0.strmOut_to_B14:ai_engine_0.DataInB1_CASC6:512
stream_connect=dma_hls_0.strmOut_to_B15:ai_engine_0.DataInB1_CASC7:512
stream_connect=dma_hls_0.strmOut_to_B16:ai_engine_0.DataInB2_CASC0:512
stream_connect=dma_hls_0.strmOut_to_B17:ai_engine_0.DataInB2_CASC1:512
stream_connect=dma_hls_0.strmOut_to_B18:ai_engine_0.DataInB2_CASC2:512
stream_connect=dma_hls_0.strmOut_to_B19:ai_engine_0.DataInB2_CASC3:512
stream_connect=dma_hls_0.strmOut_to_B20:ai_engine_0.DataInB2_CASC4:512
stream_connect=dma_hls_0.strmOut_to_B21:ai_engine_0.DataInB2_CASC5:512
stream_connect=dma_hls_0.strmOut_to_B22:ai_engine_0.DataInB2_CASC6:512
stream_connect=dma_hls_0.strmOut_to_B23:ai_engine_0.DataInB2_CASC7:512
stream_connect=ai_engine_0.DataOutC0:dma_hls_0.strmInp_from_C0
stream_connect=ai_engine_0.DataOutC1:dma_hls_0.strmInp_from_C1
stream_connect=ai_engine_0.DataOutC2:dma_hls_0.strmInp_from_C2
[advanced]
# Disable Profiling in hw_emu so that it is faster...
param=hw_emu.enableProfiling=false
Refer to this page for a detailed description of the Vitis compiler configuration file.
Switch |
Comment |
|---|---|
–connectivity.nk |
Number of kernels. |
–connectivity.stream_connect |
How the kernels connect to IP cores, platforms, or other kernels. The output of the AI Engine compiler tells you the interfaces that need to be connected. For example, |
param=compiler.addOutputTypes=hw_export |
This option tells the Vitis compiler that besides creating an XCLBIN file, it also outputs an XSA file which is needed to create a post-Vivado fixed platform for Vitis software development. |
The AMD Vitis™ compiler calls the AMD Vivado™ IP integrator under the hood to build the design. The platform and kernels are input to the Vivado Design Suite. The Vivado tool generates either a simulation XSA or an XSA after running place and route on the design. The -target option set on the Vitis compiler command line determines when the Vivado tool produces the XSA.
You can now view the Vivado project in the $(BUILD_TARGET_DIR)/_x/link/vivado/vpl/prj directory. You have now generated the XCLBIN file that your design uses to execute on the platform.