After compiling the PL HLS kernels, you can use the Vitis compiler to link them with the platform to generate an XSA file.
You integrate HLS kernels into an extensible platform provided by the hardware designer or base platforms from AMD. The Vitis tools build the hardware design and link PL kernels automatically.
To test this tutorial, use the base Versal VCK190 platform to build the design.
Use this command to run this step (the defaults are TARGET=hw_emu, N_FIR_FILTERS=1, N_FIR_TAPS=15, EN_TRACE=0):
make xsa
The expanded command is as follows:
cd build/fir_$(N_FIR_TAPS)_taps/x$(N_FIR_FILTERS)_firs/hw_emu
v++ -l \
--platform xilinx_vck190_base_202520_1 \
--include design/pl_src \
--save-temps \
--temp_dir build/fir_$(N_FIR_TAPS)_taps/x$(N_FIR_FILTERS)_firs/hw_emu/_x \
--verbose \
-g \
--clock.defaultTolerance 0.001 \
--clock.freqHz 300000000:datamover_0 \
--clock.freqHz 500000000:fir_hls_0 \
--config design/system_configs/system.cfg \
--vivado.prop run.synth_1.{STEPS.SYNTH_DESIGN.ARGS.CONTROL_SET_OPT_THRESHOLD}={16} \
--advanced.param compiler.userPostSysLinkOverlayTcl=$(DIRECTIVES_REPO)/post_sys_link.tcl \
-o vck190_hls_fir.hw_emu.xsa \
datamover.hw_emu.xo \
fir_hls.hw_emu.xo
If EN_TRACE is enabled, include the following v++ flags:
--profile.trace_memory DDR \
--profile.data datamover:datamover_0:all \
--profile.data fir_hls:dir_hls_0:all
By enabling EN_TRACE=1, timing violation occurs for ten filters with a tolerance of WNS=-0.050 set:
--xp param:compiler.worstNegativeSlack=-0.050
This captures the trace data for the ports specified.
Summary of the switches used:
Switch |
Description |
|---|---|
–platform | -f |
Specifies the name of a supported acceleration platform from |
–save-temps | -s |
Directs the |
–temp_dir |
Manages the location where the tool writes temporary files created during the build process. The compiler removes them unless you use the |
–verbose |
Displays verbose/debug information. |
-g |
Generates code for with debugging features for software emulation. Use this option to add features to help debugging the kernel during compilation. |
–clock.freqHz <freq_in_Hz>:<cu>[.<clk_pin>] |
Specifies a clock frequency in Hz and assigns it to a list of associated compute units (CUs) and optionally specific clock pins on the CU. |
–config <config_file> |
Specifies a configuration file containing |
–target | -t [hw|hw_emu] |
Specifies the build target. |
–output | -o |
Specifies the name of the output file generated by the |
–profile.data [<kernel_name>|all]:[<cu_name>|all]:[<interface_name>|all](:[counters|all]) |
Enables monitoring of data ports through the monitor IPs. Specify this option during linking. Detailed Profiling Options |
–profile.trace_memory <FIFO>:<size>|<MEMORY>[<n>] |
When building the hardware target (-t=hw), use this option to specify the type and amount of memory to use for capturing trace data. Detailed Profiling Options |
Detailed Description of All Vitis Compiler Switches Linking the Kernels in Vitis
Inputs Sources |
Description |
|---|---|
datamover.hw/hw_emu.xo |
The data-mover kernel object file. |
fir_hls.hw/hw_emu.xo |
The FIR filter chain PL kernel object file. |
Output Objects |
Description |
|---|---|
vck190_hls_fir.hw_emu.xsa |
Compiled Platform Binary Container |