As the sptag for the master and slave interfaces are the same to what was used in Part 1, there is no change to the Vitis project. It can be built using the following command:
make vitis_project RTL_OUT_BD=1
If you open the generated Vivado project, which is located under Vitis/workspace_2/system_project/build/hw_emu/hw_link/binary_container_1/binary_container_1/vivado/vpl/prj/
, you can see that the RTL AXI4-Stream interfaces have been connected to the AI Engine.