Type make aieviz to start vitis_analyzer.
Selecting Graph on the navigation bar shows a diagram of the filter implementation. It shows the data connectivity points into and out of the graph (128-bit interfaces). The design implements the symmetrical FIR filter kernel on five tiles, followed by a single tile implementing the halfband filter.
Selecting the Array option on the navigation bar shows the physical implementation of the design on the AI Engine array. The location constraints determine the tile locations.
Selecting the Trace option on the navigation bar now shows the channel filter tiles ((18,0) through (22,0)) almost fully occupied with processing the data. The computational load between the channel filter’s constituent engines now matches that of the halfband filter (23,0). The design now completes in eight iterations in ~20 µs, compared to ~44 µs.
Note: Ensure that when using trace view, you examine the waveform within the 0 to 25 µs range.