Two Tone Filter on AIE Using DSP libraries and Vitis Model Composer - 2024.1 English

Vitis Tutorials: AI Engine

Document ID
Release Date
2024.1 English

Signal Processing on AI Engine Using Vitis DSP Libraries and Vitis Model Composer

Version: Vitis 2024.1


This tutorial guides you to design an FIR filter with an FFT using the DSP library targeting AMD Versal™ AI Engine.

Before You Begin

Install the tools:

IMPORTANT: Before beginning the tutorial, make sure you have read and followed the Vitis Software Platform Release Notes (v2024.1) for setting up software and installing the VCK190 base platform.


The algorithm designer creates a MATLAB model design, which has a two tone input signal. The FIR suppresses 1-tone from a 2-tone input signal. The output of the FIR filter connects to the FFT block. This FFT block acts as a monitor to display a spectrum plot. MATLAB Model

Now the same MATLAB model will be implemented using the Vitis DSP libraries targeting AI Engine. We will build two different designs using the same IP but with different system requirements as shown below.


In design 1, the sampling rate requirement is 400 Msps, (where SSR < 1, because 400/1000 is less than 1. AI Engine clock frequency is 1 GHz).

In design 2, the sampling rate requirement is 2000 Msps (where SSR > 1 because 2000/1000 is greater than 1. AI Engine clock frequency is 1 GHz).

In both designs, the number of taps is fixed to 29 in order to achieve ~-60 dBc stop band attenuation.

Table of Contents


  • Create your DSP application using AI Engine DSP library targeting Versal AI Engine

  • Build and simulate using Vitis IDE and makefile flow

  • Implement the design using Vitis Model Composer

Tutorial Overview

This shows how to implement the two tone filter using Vitis DSP libraries targeting AI Engine. There are four parts in this tutorial:

  • Part1: Implementing design 1 (SSR<1)

  • Part2: Implementing design 2 (SSR>1)

  • Part3: Implementing design 1 using Vitis IDE

  • Part4: Implementing design 1 using Vitis Model Composer

Part 1: Implementing design 1 (SSR<1)

Designing Using the Vitis Libraries

Vitis DSP Libraries

In this step, the user needs to identify the required functions available in the DSP library. For this MATLAB model design, we need a Symmetrical FIR filter and FFT.

  • The DSPLib contains several variants of Finite Impulse Response (FIR) filters. FIR filters have been categorized into classes and placed in a distinct namespace scope:xf::dsp::aie::fir, to prevent name collision in the global scope.

  • The DSPLib contains one FFT/iFFT solution. This is a single channel, decimation in time (DIT) implementation. It has configurable point size, data type, forward/reverse direction, scaling (as a shift), cascade length, static/dynamic point size, window size, interface api (stream/window) and parallelism factor. DSP Libraries

Configure the FIR Parameters

Now, configure the FIR filter parameters based on design 1 requirements (SSR < 1). The below figure shows the FIR parameters for design 1 (SSR<1). FIR Parameters - SSR<1

  • TP_FIR_LEN is the total number of taps which is set to 29.

  • TP_CASC_LEN which describes the number of AIE processors to split the operation over, which allows resources to be traded off against performance. In this design it is set to 1.

  • TP_API is set to window type interface port.

  • TP_SSR sets a parallelism factor which is set to 1.

Configure the FFT Parameters

The below figure shows the FFT parameters for design 1 (SSR<1). FFT Parameters - SSR<1

  • TP_POINT_SIZE must be a power of 2 with a minimum value of 16. The maximum value supported by the library element is 65536, but the achievable maximum will be determined by mapping limitations. For instance, a single tile implementation can achieve a maximum of 4096, but this may require single rather than pingpong window interfaces depending on data type. It is set to 256.

  • TP_FFT_NIFFT can be set to forward or reverse transform. It is set to 1 to perform FFT.

  • TP_CASC_LEN splits the FFT/IFFT operation over multiple kernels in series, with each subsequent kernel being placed on an adjacent tile. This is to achieve higher throughput. This is set to 1.

  • TP_API is set to window type interface port.

  • TP_SSR sets a parallelism factor which is set to 1.

Passing the Parameters

Review the fir1_graph.h located under ssr_lt1/makefile_flow/src directory.

  • Observe the parameter configurations for FIR and FFT.

  • Configured parameters are passed as an argument as shown here.