This section provides an overview of the top-level VC1902 design of the MUSIC algorithm. The following diagram shows screenshots of the top-level Versal block design (BD) in IP integrator including the CIPS, NOC, DDR Interface, and AI Engine hard IPs on the left side. The Vitis Region is shown on the right side and includes three HLS kernels. Two mm2s()
kernels provide data movers to pass snapshot matrices $\textbf{A}$ from DDR to the AI Engine over two PLIO streams. A single s2mm()
kernel provides a data mover to pass the resultant MUSIC output tags back to DDR. The Vitis linker v++
has inserted clock domain crossing and data width converter IPs to match the rates from these three HLS blocks running with 128-bit I/O @ \(312.5\) MHz to the 64-bit I/O @ \(625\) MHz used by the PLIO interface to the AI Engine.
The following diagram shows the final AI Engine physical array floorplan for the MUSIC design. Some minimal floorplanning has been done to steer the kernel locations by the tools. Additional floorplanning could be done to tighten up the local tile memory placements. The tiles associated with each MUSIC subgraph have been color coded for ease of identification. The design consists of six different subgraphs: IO Adapter \((1)\), QRD \((36)\), SVD \((38)\), DOA \((64)\), Scanner \((2)\), Finder \((16)\). The full design requires a total of \(157\) compute tiles. The “snake-like” data flow is identified by arrows in the diagram. Alternative placements are possible.
The following diagram shows the final PL floorplan of the VC1902 device. Most of these highlighted resources involve circuitry required to support the base platform of the VCK190 evaluation board and are not related to the MUSIC algorithm itself.
The following diagram captures the device level resource utilization of the VC1902 device. The design is using a very small portion of the available PL resources.
Timing closure of the top-level device is achieved automatically with the standard Vitis v++
link and package flow. This is not surprising because there are only three data movers required to support the MUSIC implementation that is fully contained within the AI Engine array and no timing closure is required for this hardened portion of the design.