Timing Closure - Timing Closure - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

For timing closure of the whole design, different implementation properties are used, as mentioned in the make xsa step in the preceding section. The design requires these strategies because timing is not met for default implementation settings. Routing congestion limits operating frequency to 700 MHz.

For more information about implementation strategies, refer to the Vivado Implementation User Guide (UG904).