After a Vivado design is created, Vivado then goes through the design implementation process. This process involves placement, routing, and physical optimization.
Placement is placing the specified ports and logic cells onto device resources.
Routing routes the nets in the design to complete logic connections on the target part.
Physical optimization performs timing-driving optimization on negative-slack paths of a design.
Large platforms often require Tcl commands before and after these design implementation steps to guide the Vivado tool to generate4 a timing closed implementation.
The next part of the vck_190_v1_0_xsa.tcl script sets the place_design, route_design, and phys_opt_design pre- and post- Tcl hooks to specific scripts that help close timing during implementation.
The pre_place.tcl script calls the prohibitCascBramAcrossRbrk.tcl, prohibitCascUramAcrossRbrk.tcl, and prohibitCascDspAcrossRbrk.tcl scripts which prohibit the cascading the BRAM, URAM, and DSP resources. It also calls the waive_BLI_AIE_timing_violations_preplace.tcl script, which allows the timing violations between the BLI registers and AI Engine before placements.
The post_place.tcl script calls the waive_BLI_AIE_timing_violations_postplace.tcl, which allows timing violations between the BLI register and the AI Engine after placement.
The post_route.tcl and the post_physopts.tcl scripts are empty because this beamforming tutorial does not require Tcl commands after routing and physical optimization. These scripts are provided for you to add commands if you wish to modify this tutorial.