There are many different ways to close timing. This section explains how timing closure is approached in the beamforming design.
Identify the problematic paths causing negative slack. The longest paths in the design are between the PL kernels and AI Engine, which cannot operate at 400 MHz clock frequency without negative slack.
Break up these paths and reduce the amount of time it takes to get from the PL kernel to the AI Engine. You can do this by introducing two AXI register slice IPs in the paths to pipeline the data flow.
In addition, apply timing closure strategies during each stage of implementation: placement, routing, and physical optimization. The full list of strategies available for each stage is documented in Vivado Design Suite User Guide Implementation Chapter 2: Implementing the Design (UG904).