In this test case each 2D tile is divided by 4 (2x2) read columnwise then rowwise. Each layer and Image is read one after the other. The 2 last dimensions can be seen as a single layer dimension of size 16.
The write access is done as a single block, and the read access defines the specific access order:
uint D01 = Dim0 * Dim1; // 64
uint D23 = Dim2*Dim3; // 16
uint D0123 = D01 * D23; // 1024
adf::write_access(mtxin.in[0]) =
adf::tiling({.buffer_dimension = {D0123}, // 1024
.tiling_dimension = {D0123}, // 1024
.offset = {0},
.tile_traversal = {}});
adf::read_access(mtxin.out[0]) =
adf::tiling({.buffer_dimension = {Dim0, Dim1, D23}, // 8, 8, 16
.tiling_dimension = {(Dim0 / 2), (Dim1 / 2), 1}, // 4x4x1
.offset = {0, 0, 0},
.tile_traversal = {
{.dimension = 0, .stride = Dim0 / 2, .wrap = 2}, // Dim0/2 = 4
{.dimension = 1, .stride = Dim1 / 2, .wrap = 2}, // Dim1/2 = 4
{.dimension = 2, .stride = 1, .wrap = D23}}});
This partition is very simple. Let’s compile this graph:
make SECTION=memtile T1 aie
This ends up with this error message
INFO: [aiecompiler 77-6570] For port 'TG.G1.mtxin.in[0]', allocated DMA is 'tile: memory, col:10, row:0, channel:0, dir:s2mm'
INFO: [aiecompiler 77-6570] For port 'TG.G1.mtxin.out[0]', allocated DMA is 'tile: memory, col:10, row:0, channel:0, dir:mm2s'
ERROR: [aiecompiler 77-4352] Failed to allocate buffer descriptors for TG.G1.mtxin due to insufficient number of available buffer descriptors.
Tiling parameters are specified but the error message states that the number of Buffer Descriptors (BD) is insufficient.
Let’s count the number of buffer descriptors needed for these read and write accesses: