Test Case 4 - 2025.1 English - XD100

This last test case shows a zero padding on dimension 1. There are 64 channels (dimension 0) containing each 512 samples. The kernel cannot absorb the totality of the samples so the processing is divided along the channels and the samples dimension. Along the dimension 1 zero-padding is activated to allow filtering along this dimension:

const uint D0 = 64;
const uint D1 = 512;
int Pad = 4;
const uint Tile0 = 8;
// const uint Tile0 =16;
const uint Tile1 = 4;
 mtxin = adf::shared_buffer<int32>::create({D0*D1}, 1, 1);
 adf::connect(din, mtxin.in[0]);
adf::write_access(mtxin.in[0]) = adf::tiling({
        .buffer_dimension = {D0*D1},
      .tiling_dimension = {},
      .offset = {0, 0},
      .tile_traversal = {}});

// Original data sent layer by layer
adf::connect(mtxin.out[0], k1.in[0]);
adf::read_access(mtxin.out[0]) = adf::tiling({
        .buffer_dimension = {D0,D1}, // 64x512
       .tiling_dimension = {Tile0,Tile1}, // 8x8
       .offset = {0, -Pad},
       .tile_traversal = {
           {.dimension = 1, .stride = Tile1, .wrap = (D1+2*Pad)/Tile1},
           {.dimension = 0, .stride = Tile0, .wrap = D0/Tile0}}});

If you try to compile as is (Tile dimensions: 8x4), you’ll get an error because of an insufficient number of BDs.

make SECTION=memtile data T4 aie

Vertically we need 3 BD’s:

• one for the top with the zero-padding (wrap=1)

• one for the middle part with a wrap of 128

• one for the bottom with the zero padding (wrap = 1)

As the width (dimension 0) is 64 with a width of 8, this means a wrap of 8, hence 3 (vertical BDs) x 8 (to process all columns) x 2 (even and odd phase) = 48 BDs.

That is twice as much as what is available in the Memory Tile for a channel. Changing the Tile size to 16x4 will reduce to 24 BDs which is just OK.

Change:

const uint Tile0 = 8;
// const uint Tile0 =16;

into

//const uint Tile0 = 8;
const uint Tile0 =16;

Recompile and run simulation.