In this case, data reordering is too complex to be handled on a single Memory Module. The output buffer of Kernel 1 is read tile by tile from the output buffer and written stripe by stripe on the input buffer of kernel 2:
adf::read_access(k1.out[1]) = adf::tiling(
{.buffer_dimension = {Dim0, Dim1},
.tiling_dimension = {4,2},
.offset = {0, 0},
.tile_traversal = {
{.dimension = 1, .stride = 2, .wrap = Dim1/2},
{.dimension = 0, .stride = 4, .wrap = Dim0/4}}});
adf::write_access(k2.in[0]) = adf::tiling(
{.buffer_dimension = {Dim0, Dim1},
.tiling_dimension = {1, 8},
.offset = {0, 0},
.tile_traversal = {
{.dimension = 0, .stride = 1, .wrap = Dim0}}});
The aiecompiler automatically inserts a stream communication in between the output buffer of k1 and the input buffer of k2. All these data manipulation are done automatically by the DMAs, leaving the AI Engine compute performance for data processing only.
Compile and run simulation:
make data T2 x86 x86sim
And check the output:
Utils/GetTiles.py memmodule_x86simulator_output/data/Output_0.txt 2D 8 8 0 1
to get the original data organization:
Tile: 0
0 1 2 3 4 5 6 7
10 11 12 13 14 15 16 17
20 21 22 23 24 25 26 27
30 31 32 33 34 35 36 37
40 41 42 43 44 45 46 47
50 51 52 53 54 55 56 57
60 61 62 63 64 65 66 67
70 71 72 73 74 75 76 77
Type:
Utils/GetTiles.py memmodule_x86simulator_output/data/Output_1.txt 2D 8 8 0 1
to get the modified data organization:
Tile: 0
0 20 40 60 4 24 44 64
1 21 41 61 5 25 45 65
2 22 42 62 6 26 46 66
3 23 43 63 7 27 47 67
10 30 50 70 14 34 54 74
11 31 51 71 15 35 55 75
12 32 52 72 16 36 56 76
13 33 53 73 17 37 57 77