The graph code for the TDM mixer targets full-speed operation above 1000 MSPS.
The design uses templates to support NSAMP I/O samples and CC channels. Ensure NSAMP is a multiple of eight to match the vectorization. Ensure CC is a multiple of four to match assumptions of the final optimized code outlined in the following figure.
The graph encapsulates a single AI Engine tile that runs the mixer kernel. The design supplies I/O data over a single programmable logic input/output (PLIO) stream. The design uses I/O buffers sized NSAMP * CC samples with default double buffering. In this example, configure mixer frequencies statically using the tdm_mixer_phase_inc.h included header file.
At graph level, two programming model elements handle corner-turning operations in the data flow. Two tiling_parameters structures define the settings. The bdw instance configures the input buffer corner-turning. The bwr instance configures the output buffer corner-turning.
Associate these tiling parameters with specific kernel I/O ports by adding annotations. For example, kernel input port kk.in[0] uses the bdw tiling parameter in Line 55. This specifies the write_access of the port is controlled by tiling(bdw). Similarly, Line 56 specifies the read_access of kernel output port kk.out[0] is controlled by tiling(bdr).