The graph code for the TDM mixer is shown below. The goal is to produce a TDM mixer that runs at full speed > 1000 Msps.
Notice the design is templated to support NSAMP I/O samples and to support a total of CC channels. NSAMP must be a multiple of 8 to match the vectorization. CC must be a multiple of 4 to match the assumptions of the final optimized code outlined below.
The graph encapsulates a single AI Engine tile implementing the mixer kernel. The design supplies I/O data over a single PLIO stream. The design uses I/O buffers of size NSAMP * CC samples with default double buffering. For simplicity in this example, the mixer frequencies are configured statically via the tdm_mixer_phase_inc.h included header file.
Notice the two programming model elements used at the graph level to incorporate the corner-turning operations required by the data flow. There are two tiling_parameters data structures. The bdw instance configures the corner-turning for the input buffer. The bwr instance configures the corner-turning for the output buffer. These tiling parameters become associated with particular buffers by annotating the associated kernel I/O ports. Notice how kernel input port kk.in[0] becomes annotated with the bdw tiling parameter through Line 55: this specifies the write_access of this port will be governed by tiling(bdw). Similarly in Line 56: the read_access of kernel output port kk.out[0] will be governed by the bdr tiling parameter through tiling(bdr).