The streaming interface is based on two incoming streams and two outgoing streams, each one on 32 bits per clock cycle. These four streams are handled by a stream FIFO that allows the processor to use different bitwidths to access these streams:
2 streams in, 2 streams out:
Each one 4 bytes/cycle or 16 bytes/ 4 cycles
Parallel access to streams per VLIW:
2 reads (4/16 bytes), 1 write (4/16 bytes)
OR 1 read (4/16 bytes), 2 writes (4/16 bytes)
Using 1 stream:
4 bytes/cycle read and 4 bytes/cycle write
Using the 2 streams and the 16-byte access option:
Reads and/or writes can be dispatched over time
On an average 8 bytes/cycle read and 8 bytes/cycle write
Accessing the data to/from the streams using the 128-bit interface does not increase the bandwidth, but limits the number of accesses that must be scheduled within the microcode of the VLIW processor.