Step 3 - Interfacing the ADF Graph to the Programmable Logic - Step 3 - Interfacing the ADF Graph to the Programmable Logic - 2025.2 English - XD100

To interface the ADF graph to the polar_clip RTL kernel and the mm2s and s2mm HLS kernels, add connections between PLIOs and the corresponding PL kernels IOs.

1. The following graph.h shows how to connect to the RTL kernel.

     adf::source(interpolator) = "kernels/interpolators/hb27_2i.cc";
     adf::source(classify)    = "kernels/classifiers/classify.cc";
     
     //Input PLIO object that specifies the file containing input data
     in = adf::input_plio::create("DataIn1", adf::plio_32_bits,"data/input.txt");
     clip_out = adf::input_plio::create("clip_out", adf::plio_32_bits,"data/input2.txt");
     
     //Output PLIO object that specifies the file containing output data
     out = adf::output_plio::create("DataOut1",adf::plio_32_bits, "data/output.txt");
     clip_in = adf::output_plio::create("clip_in",adf::plio_32_bits, "data/output1.txt");
   
     connect(in.out[0], interpolator.in[0]);
     connect(interpolator.out[0], clip_in.in[0]);
     connect(clip_out.out[0], classify.in[0]);
     connect(classify.out[0],out.in[0]);
   

   Note the following:

   • Two additional PLIO objects clip_in and clip_out are added. These hook up to the polar_clip RTL kernel.

   • There are additional net objects to hook up the RTL kernel to the rest of the platform object.

   For more information on RTL kernels in the AI Engine, refer to Integrating AIE and PL Components.

2. Compile the graph using the following command:

   v++ --mode aie -c  --target=hw --include="/include" --include="./aie" --include="./data" --include="./aie/kernels" --include="./"  --aie.workdir=./Work --platform=${XILINX_VITIS}/base_platforms/xilinx_vck190_base_202520_1/xilinx_vck190_base_202520_1.xpfm aie/graph.cpp
   

   or

   make aie