Stage 3: Generate the Code and Perform Emulation-AI Engine - Stage 3: Generate the Code and Perform Emulation-AI Engine - 2025.2 English - XD100

In this stage, you generate the graph code of this design and perform bit-true and cycle-approximate simulations with the AI Engine Simulator.

1. Select the four AIE FIR Filters and the Frequency shifting block, and type CTRL+G to group them in a subsystem. Assign a new name: FIRchain.

2. Double-click the block Model Composer Hub and select the Code Generation tab.

3. Select the FIRchain subsystem, and set the following parameters on the Analyze tab:

   • Check Collect profiling statistics and enable ‘printf’ for debugging.

   • Check Collect trace data for Vitis Analyzer, view internal signals, and latency.

4. Click Analyze.

Run the Simulink® design to generate the testbench. Generate and compile the graph code. View the source code in ./code/ip/FIRchain/src/FIRchain.h:

#ifndef __XMC_FIRCHAIN_H__
#define __XMC_FIRCHAIN_H__

#include <adf.h>
#include "./FIR_Halfband_Decimator_e52f70d5/FIR_Halfband_Decimator_e52f70d5.h"
#include "./FIR_Halfband_Decimator_5d110589/FIR_Halfband_Decimator_5d110589.h"
#include "./FIR_Halfband_Decimator_f09fd8f2/FIR_Halfband_Decimator_f09fd8f2.h"
#include "./FIR_Asymmetric_da0a14e6/FIR_Asymmetric_da0a14e6.h"
#include "aiecode_src/FreqShift.h"

class FIRchain_base : public adf::graph {
public:
   FIR_Halfband_Decimator_e52f70d5 FIR_Halfband_Decimator;
   FIR_Halfband_Decimator_5d110589 FIR_Halfband_Decimator1;
   FIR_Halfband_Decimator_f09fd8f2 FIR_Halfband_Decimator2;
   FIR_Asymmetric_da0a14e6 FIR_Asymmetric;
   adf::kernel FreqShift_0;

public:
   adf::input_port In1;
   adf::output_port Out1;

   FIRchain_base() {
      // create kernel FreqShift_0
      FreqShift_0 = adf::kernel::create(FreqShift<256>);
      adf::source(FreqShift_0) = "aiecode_src/FreqShift.cpp";

      // create kernel constraints FreqShift_0
      adf::runtime<ratio>(FreqShift_0) = 0.9;

      // create nets to specify connections
      adf::connect net0 (In1, FIR_Halfband_Decimator.in[0]);
      adf::connect net1 (FIR_Halfband_Decimator.out[0], FIR_Halfband_Decimator1.in[0]);
      adf::connect net2 (FIR_Halfband_Decimator1.out[0], FIR_Halfband_Decimator2.in[0]);
      adf::connect net3 (FIR_Halfband_Decimator2.out[0], FIR_Asymmetric.in[0]);
      adf::connect net4 (FIR_Asymmetric.out[0], FreqShift_0.in[0]);
      adf::dimensions(FreqShift_0.in[0]) = {256};
      adf::connect net5 (FreqShift_0.out[0], Out1);
      adf::dimensions(FreqShift_0.out[0]) = {256};
   }
};

class FIRchain : public adf::graph {
public:
   FIRchain_base mygraph;

public:
   adf::input_plio In1;
   adf::output_plio Out1;

   FIRchain() {
      In1 = adf::input_plio::create("In1",
            adf::plio_32_bits,
            "./data/input/In1.txt");

      Out1 = adf::output_plio::create("Out1",
            adf::plio_32_bits,
            "Out1.txt");

      adf::connect< > (In1.out[0], mygraph.In1);
      adf::connect< > (mygraph.Out1, Out1.in[0]);
   }
};

#endif // __XMC_FIRCHAIN_H__

Finally, the bit-exact simulation (Emulation-AIE) is performed and the result compared to the Simulink simulation:

5. In the Model Composer Hub, click Open Vitis Analyzer.

Vitis Analyzer launches and you can view the Graph View, Array View, Trace View, and Profile information.

Vitis Model Composer can also plot the output of the cycle-approximate AI Engine simulation and calculate a throughput estimate. AI Engine calculates throughput by counting the number of output data points and dividing by the time. In this example, three frames are received, but only two interframe idle time are counted. To obtain a more accurate throughput estimate, you can use data cursors to select a specific time region over which to calculate throughput:

6. In the Model Composer Hub, click View AIE Simulation output and throughput. The Simulation Data Inspector opens and shows the output of the AI Engine.

7. Select the Out1 signal from the list on the left.

8. Click the drop-down of a plot icon, then select the Two cursors option.

   

9. Position the cursors at the beginning of the first and third signal frames, as shown below.

Here the estimated throughput is 28 MSPS instead of the expected 125 MSPS. You can use Vitis Analyzer to track the reason of this throughput reduction. The input stream feeds the data at 250 MSPS instead of the 1000 MSPS specified in the design. This occurs because the input bitwidth is 32 bits at a rate of 250 MHz by default. Confirm this setting at the end of the FIRchain.h file.