In this new example, two branches receive data from the same PLIO and connect on the output side to a kernel that computes the difference between the two branch outputs.
VERSION=3 of this design stalls almost immediately because this design needs FIFOs set up at the input and output of each branch.
VERSION=4 sets these FIFOs and the overall simulation lasts approximately 275 µs. This one does not work for AI Engine-ML as the FIFO is too large for this architecture.