After the graph has been compiled, you can simulate your design with the aiesimulator
command. This uses a cycle-approximate model to test your graph and get preliminary throughput information early in the design cycle, while the PL developers continue to work on the platform for the application.
Note: Simulating the design with VCD will increase simulation runtime. To learn more about this feature, see AI Engine SystemC Simulator.
To run simulation use the command:
make sim TARGET=hw
or
aiesimulator --profile --dump-vcd=tutorial --pkg-dir=./Work
| Flag | Description |
| ---- | ----------- |
| --profile | Profiles all kernels, or select kernels (col,row)...(col,row).|
| --dump-vcd | Grabs internal signals of tiles and dumps it in a VCD file. |
| --pkg-dir | The ***Work*** directory. |
When simulation has completed, use a terminal to navigate to the
aiesimulator_output
directory by running:cd aiesimulator_output; ls
You should see something similar to this:
aiesim_options.txt profile_funct_24_0.xml profile_funct_25_0.xml profile_instr_24_0.xml profile_instr_25_0.xml data profile_funct_24_1.txt profile_funct_25_1.txt profile_instr_24_1.txt profile_instr_25_1.txt default.aierun_summary profile_funct_24_1.xml profile_funct_25_1.xml profile_instr_24_1.xml profile_instr_25_1.xml profile_funct_24_0.txt profile_funct_25_0.txt profile_instr_24_0.txt profile_instr_25_0.txt
The files prefixed with
profile_
are the outputs of the profiling and calculated per tile. In this tutorial, profiling is done for all tiles that are used, but you can limit profiling to specific tiles by providing the row and column of the tile. For more information about profiling withaiesimulator
see here. You can open up these files to see what was calculated, but it is better to view it in Vitis Analyzer where it is curated. Thedata
directory is generated here with the output file(s) you have in thegraph.cpp
for the PLIO objects. Finally, thedefault.aierun_summary
is generated, which contains all the information generated byaiesimulator
with profiling and trace information. Opening this file in Vitis Analyzer allows you to browse all the output files, and profile/trace data.NOTE: The
tutorial.vcd
is generated on the same level as the./Work
directory.You can now open the generated
default.aierun_summary
from theaiesimulator_output
directory for Vitis Analyzer.To do this,run the command:
vitis_analyzer -a ./aiesimulator_output/default.aierun_summary
With this tool you can use a variety of views to debug and potentially optimize your graph.
The Summary view provides an overview of running
aiesimulator
. As you can see in the following figure, it provides information on status, version used, time, platform used, and the command line used to execute.Click Profile.
The Profile View provides detailed information collected during the simulation. Information includes cycle count, total instructions executed, program memory, and specific information per functions in the two tiles that the kernels are programmed.
This is the top-level view of the profile. The left column allows you to select one of many types of reports generated per function.
Select the first Total Function Time from this column. You will see the following.
In this chart you can see what function is called most, function time, etc. This information can be useful in determining if the tile is under- or over-utilized in your design.
Click Graph.
The Graph view provides an overview of your graph and how the graph is designed in a logical fashion. In this view, you can see all the PLIO ports, kernels, buffers, and net connections for the entire ADF Graph.
Note: This view, as well as the Array view have cross-probe selection, meaning selecting an object in this view will select it in the other and vice versa.
Click Array.
The Array view provides a logical device view of the AI Engine, kernel placement, and how they are connected to each other as well as the shim.
Cross probe to kernel and graph source files.
The table at the bottom shows the following:
Kernel - The kernels in the graph.
PL - Shows connections between the graph and PLIO.
Buffer - Shows all the buffers used for inputs/outputs of the graph and the buffers for kernels.
Port - Shows all the ports of each kernel and ADF Graph.
Net - Shows all nets, named and generated, mapped in the ADF Graph.
Tile - Shows tile data (kernels, buffers) of mapped tiles and their grid location.
Tip: For more detailed information about these tables, see Section: “Viewing Compilation Results in the Vitis Analyzer”.
You can zoom into the view to get finer detail of the AI Engine and see how tiles are made up as seen in the following screenshot.
To zoom in, click and drag from the upper-left to the lower-right of the area you want to view to have a box show up around the area to zoom. Below is a zoomed-in area.
In this zoomed in location you can see how the kernels are connected to a variety of tiles and how the shim is connected to the PLIO ports of this design.
Click Simulator Output.
Finally, the Simulator Output view. This will print out the
output.txt
generated by the graph. This is a timestamped output.Note: If you need to compare this file to a golden one, you will need have to remove the -
T ####ns
- from the file.If you need to make any changes to the ADF Graph or the kernels inside based on results of the
aiesimulator
you can do so and re-run the compiler and view the results in Vitis Analyzer to see the changes you have made.When you are done with Vitis Analyzer, close it by clicking File > Exit.