Placement Constraints - Placement Constraints - 2026.1 English - XD100

This design employs the “Stamp and Repeat” placement methodology to achieve the regular floorplan shown. In this case, the design adopts the JSON constraints file approach rather than resorting to putting placement constraints in the graph code. The aie_top_8engine_app.aiecst file located here contains the constraints. Some important considerations are as follows:

• The NodeConstraints on Line 2 put tile constraints on the iFFT portion of the design to assist the router in finding a solution. The placement provides sufficient room at the top of the columns for the heavy memory footprint of these kernels.

• The GlobalConstraints on Line 18 contain the “Stamp & Repeat” constraints for the 8-engine design. Here, the isomorphicGraphGroup identifies the referenceGraph as “engine0” and the stampedGraphs as “engine1” through “engine7.” The following lines define the desired areaGroup placements for each engine in terms of the desired tileGroup and shimGroup, respectively. This enables a set of common tile rectangles to be defined, where a common placement is applied from the “engine0” solution to the remaining engines in the design.

• The mapper/router performs the back-end solution because all placement for “engine0” was solved previously, and is simply copied across all the remaining engines.