AI Engine compilation in phase 1 generates numerous files in the Work directory. The Work/temp/graph_aie_routed.aiecst file contains all the constraints that you can use during AI Engine compilation to get the exact same placement. From this file, remove the constraints related to the programmable logic input output (PLIO) interface nodes, removing the other nodes and all the port constraints:
{
"NodeConstraints": {
"DataIn1": {
"shim": {
"column": 24,
"channel": 0
}
},
"clip_in": {
"shim": {
"column": 24,
"channel": 0
}
},
"clip_out": {
"shim": {
"column": 25,
"channel": 0
}
},
"DataOut1": {
"shim": {
"column": 25,
"channel": 0
}
}
}
}
Phase 2 contains the following stages:
aie2: As in the previous phase, this stage builds an AI Engine application, but in this case, it uses new interface constraints. The kernel itself has not changed but a kernel location constraint is added to the graph so that you can see a big difference in the kernel placement. Check this new placement using Vitis Analyzer on the compile summary.package2: Create the PDI to load onto the device (hw_emu).run_emu: Launch the simulation and verify that the output is still correct.
Run make phase2 to go over all steps. Simulate the design as in phase 1. Expect a longer runtime due to the extended routing path.