Considering that input requires six floating-point values per pixel while output is a single floating-point value, it is apparent that the input stream places a more restrictive limit on achievable pixel processing rate. The PLIO interface supports transfer rates of one floating-point value per cycle, which depending on speed grade of the AMD Versal™ device, amounts to transfer rates of 1.0 to 1.25 billion floating-point values per second. Because the input requires six floating-point values per pixel, the input PLIO restricts the rate to 6.0 cycles per pixel. To more closely match the input limitation to computational efficiency, three input PLIO interfaces are used. This brings the limitation down to 2.0 cycles per pixel. Figure 7 shows the data format for each of the input PLIO interfaces.
Figure 7 - Input PLIO Data Format