Output Buffer Tiling Parameters - Output Buffer Tiling Parameters - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

The bdr tiling parameter defines how the stream DMA reads output samples from the kernel output buffer. This works the same as the bdw tiling parameter, except writing and reading functions swap roles.

The AI Engine tile writes output samples along dimension‑0 of a default one-dimensional (1D) buffer because no write‑access tiling parameter is specified. Therefore, the kernel writes by columns, and the output DMA reads by rows.