The bdr tiling parameter governs how output samples are read from the kernel output buffer by the stream DMA. This operates in a manner identical to the ‘bdw’ tiling parameter outlined above except the roles of writing and reading are swapped. Note the AI Engine tile will also write output samples along dimension-0 of a default 1D buffer as no write access tiling parameter is specified. So the kernel writes by columns and the output DMA needs to be read by rows.