Memory interface - 2024.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2024-12-06
Version
2024.2 English

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Each AI Engine is surrounded by 4x 32 kB memories, each one being divided in four pairs of banks. The bandwidth is high:

  • 2 reads / cycle on 32 bytes (256 bits) each

    • Each bank has a single port, the accesses must be done on different banks to achieve 2x 256 bits/cycle.

  • 1 write / cycle on 32 bytes (256 bits)

    • On another bank to achieve the highest bandwidth.

  • Be aware that you need also to feed the memories using DMAs or other AI Engines.