Introduction - Introduction - 2026.1 English - XD100

The Fractional Delay Farrow Filter design already exists for the AIE and AIE-ML architectures. This tutorial shows you how to migrate the global memory input/output (GMIO)-based design from the AIE-ML architecture to the AIE-ML v2 architecture.

A fractional delay filter is a common digital signal processing (DSP) algorithm used in many applications, including digital receivers in modems, for timing synchronization.

Before porting to the AIE-ML v2 architecture, learn the Farrow Filter and its implementation details with the AIE architecture.

Study the tutorial Fractional Delay Farrow Filter Targeting AIE Architecture to understand the following:

1. What is a farrow filter?

2. Requirements and AIE system partitioning

3. AI Engine implementation and optimization

Review Migrating Fractional Delay Farrow Filter from AIE to AIE-ML Architecture to learn migration methods. Port the GMIO-based farrow filter design from the AIE-ML tutorial to the AIE-ML v2 architecture.

The GMIO-based farrow filter design from AIE-ML makes use of the GMIO ports. A GMIO port attribute creates external memory‑mapped connections to or from global memory. These connections link AI Engine kernels to logical global memory ports within a hardware platform design. To learn more about how to implement the GMIO interface, review the kernel written in the graph and test bench (farrow_graph.h and farrow_app_adf.cpp) located in the <path-to-tutorial>/designs/aie_ml/ directory.

After reviewing the background on the farrow filter design in AIE and AIE-ML, begin porting the design to the AIE-ML v2 architecture. The design requirements remain identical because you are migrating the design to AIE-ML v2 architecture:

Requirements
Sampling rate	1 GSPS
I/O data type	cint16
Coefficients data type	int16
Delay input data type	int16

IMPORTANT: Before starting the tutorial, read and follow the Vitis Software Platform Release Notes (v2026.1) to set up the software and install the VEK385 base platform.

Run the following steps:

1. Set the YOCTO_ARTIFACTS environment variable to the AMD EDF from the embedded platforms download page EDF Packages.

2. Set the PLATFORM_REPO_PATHS environment variable to the location where you downloaded the platform.

Follow these instructions to port the design from AIE-ML on VEK280 to AIE-ML v2 on VEK385:

• Change platform in Top Makefile from xilinx-vek280_base to vek385_base.

• For Versal AI Edge Series Gen 2, AMD tools default to Segmented Configuration and AMD Embedded Development Framework (EDF).

• Segmented configuration boots processors in a Versal device and accesses double data rate (DDR) memory before configuring the programmable logic (PL). Boot using a primary firmware image, such as the pre‑built VEK385 EDF boot firmware Image (OSPI) Image from Versal AI Edge Series Gen 2 VEK385 HeadStart Board Early Access Secure Site. Use a secondary image built with Yocto Linux, found in the same location as EDF Linux® BSP Common SD-Card Image for Cortex A78 devices. Generate the device tree overlay pl.dtbo, using sdtgen and lopper. After completing these steps, transfer the necessary files to boot and run the design on hardware using scp. Load pl-aie.pdi and the device tree using fpgautil. Execute the host program, pointing to dut.xclbin, to run the design on hardware.