Input Buffer Tiling Parameters - 2025.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2025-08-25
Version
2025.1 English

The bdw tiling parameter governs how input samples are written into the kernel input buffer by the stream DMA.

Firstly, the buffer_dimension is defined. Both 1D and 2D buffers are supported. To effect a corner-turn, you must define a 2D buffer with dimension-0 defined as NSAMP samples and dimension-1 as CC samples. This defines the physical extent of the buffer.

The tiling descriptor operates using a concept of “tiles” which can be of dimension $M\times N$ samples. For a simple corner-turn, use a single sample tile with tiling_dimension of {1,1}, with each tile containing a single sample.

The DMA hardware will write these “tiles” into the buffer in an order prescribed by the tile_traversal that specifies three quantities for each buffer_dimension. The first quantity is the next dimension to process, the second quantity is the stride to take (measured in samples) before writing the next “tile”, and the third quantity instructs the DMA engine to wrap its address back to zero when it reaches this many “tiles”. The offset parameter can be used to introduce a starting offset (in each buffer dimension) for the DMA addressing. This feature is not required for corner-turning.

The bdw tiling parameter in Line 42 prescribes the following data flow (see [2] for additional details):

  • The input buffer will be 2D with dimensions {NSAMP,CC} with zero offsets in each dimension.

  • The DMA will operate on tiles with a single sample.

  • The DMA will write into dimension-1 first (along the rows) advancing one sample/tile at a time, wrapping around to zero after CC samples.

  • The DMA will then advance one sample/tile along dimension-0, and then continue processing along dimension-1 for the remainder of that row.

  • The DMA will wrap around to zero in dimension-0 after NSAMP samples.

Clearly, this tiling parameter causes the DMA to write samples by rows (dimension-1) into the buffer. To effect the desired corner-turn, the AI Engine kernel must then read samples by columns (dimension-0) from the buffer. Because no read access tiling parameter is specified by the input buffer, it defaults to a 1D buffer of size NSAMP*CC and will read along dimension-0 which is exactly what is needed.