Input Buffer Tiling Parameters - Input Buffer Tiling Parameters - 2025.2 English - XD100

The bdw tiling parameter defines how the stream DMA writes input samples into the kernel input buffer.

First, define the buffer_dimension. You can use either 1D or 2D buffers. To perform a corner-turn, define a 2D buffer with dimension-0 equal to NSAMP samples and dimension-1 equal to CC samples. This sets the physical extent of the buffer.

The tiling descriptor uses tiles, each containing \(M\times N\) samples. For a simple corner-turn, use a single-sample tile with tiling_dimension set to {1,1}. The DMA hardware writes tiles in the order specified by the tile_traversal, which specifies three values for each buffer_dimension:

• The next dimension to process.

• The stride in samples before writing the next tile.

• The wrap count in tiles when the address resets to zero.

You can use the offset parameter to start addressing from a nonzero index in each buffer dimension. Corner-turning does not require an offset.

The bdw tiling parameter in Line 42 defines the following data flow (refer to [2] for details):

• The input buffer is 2D with dimensions {NSAMP,CC} and zero offsets.

• The DMA processes single-sample tiles.

• The DMA writes into dimension-1 first (along the rows), advancing one sample at a time and wrapping to zero after CC samples.

• The DMA then advances one sample along dimension-0, then continues across dimension-1 for the rest of the row.

• The DMA wraps to zero in dimension-0 after NSAMP samples.

This configuration causes the DMA to write samples row-by-row (dimension-1) into the buffer. To perform the desired corner-turn, the AI Engine kernel reads samples column-by-column (dimension-0) from the buffer. Because the input buffer has no read-access tiling parameter, it defaults to a 1D buffer of NSAMP*CC samples, reading along dimension-0 (exactly what is needed).