While an SSR=5 is sufficient from a resource count perspective, using a SSR that is a power of 2 simplifies the overall design and allows the direct mapping of TDM FIR outputs into 2D IFFT input. For this reason, we proceed with SSR=8.
We can also apply the single_buffer constraint on some I/Os of this block to reduce the storage requirements at the expense of some degradation in throughput. Using single_buffer on the I/Os of the front FFT and on the input of the back FFT lets you place the design in a compact (8x2) placement.
[shell]% cd <path-to-design>/aie/ifft4096_2d
[shell]% make gen_vectors
[shell]% make clean all
[shell]% vitis_analyzer aiesimulator_output/default.aierun_summary
Inspecting vitis_analyzer, we observe a resource count of 16 AIE-ML tiles and 6 Memory Tiles. Achieved throughput for:
Front 64-point IFFT + point-wise twiddle multiplication = 2386 MSPS
Back 64-point IFFT = 2376 MSPS
The AI Engine portion of the design is implementing the front/back transpose operations. What remains is the middle transpose block, done in PL.
The IFFT mid transpose block that exist in ${DSPLIB_ROOT}/L1/src/hw/mid_transpose. The PL runs at 312.5 MHz and use 128-bit interfaces. A 128-bit interface contains two cint32 samples, so instantiate this block with 2x SSR value selected for AIE portion, that is, 16. A PL splitter/merger block must connect on each side of this transpose block to match these SSR assumptions. These exist in ${DSPLIB_ROOT}/L1/src/hw/common_fns/axis_split_join.