Compile and simulate the design to confirm it works as you expect.
[shell]% cd <path-to-design>/aie/ifft4096_2d
[shell]% make clean all
[shell]% vitis_analyzer aiesimulator_output/default.aierun_summary
Inspecting vitis_analyzer, note the resource count of 16 AIE-ML v2 tiles.
Achieved throughput for:
Front 64-point IFFT + point-wise twiddle multiplication = 2731 MSPS
Back 64-point IFFT = 3436 MSPS
Performance Comparison with Original Design:
Metric |
Original (AIE-ML) |
Ported (AIE-ML v2) |
Improvement |
|---|---|---|---|
Front 64-pt IFFT + Twiddle |
2386 MSPS |
2731 MSPS |
+14% |
Back 64-pt IFFT |
2376 MSPS |
3436 MSPS |
+45% |
AI Engine Tiles |
16 |
16 |
Same |
Memory Tiles |
6 |
7 |
+1 |
Note: Minor difference in the number of memory tiles. This is due to the different design floorplan and the different number of available rows.